Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DrMrLordX]

Beyond it being pretty weird IMO to downplay 18A for "just" being a 3 nm class node. A few years ago Intel barely even had a 7nm "competitor" while TSMC was rolling out N4P, and now Intel shipping a process that's at worst roughly on par with N3P,

Is 18A really on par with N3P? 18AP sure, but 18A?

 

[Magio]

Is 18A really on par with N3P? 18AP sure, but 18A?

The efficiency figures (if the slides turn out to be accurate, of course) from PTL vs ARL/LNL on N3B make me think it's in the ballpark at least. The peak performance figures are another story but there's a caveat with that IMO: We don't know how much of it is the P-core being a bottleneck. Because Raptor Lake refresh on Intel 7 delivers the same peak perf as LNL/ARL so either Intel 7 = N3B = 18A or Intel's P core is hot garbage and can't scale anymore. And since Intel can't score clients yet sadly that P core is our only measure of peak performance but I don't think it's an accurate one. So pending more data I feel like putting 18A and N3P in the same basket is reasonable if efficiency figures are confirmed.

Of course there are two elephants in the room (which is too many elephants) with that still: Yields and volume, because even if 18A is indeed N3P level or better it's nowhere close to it in either of those aspects. So Intel Foundry has work to do still for sure but my point was that downplaying 18A when it's the closest Intel has been to the leading edge since TSMC shipped N7 in 2018, or downplaying technical wins like BSPDN is just pushing the negativity a bit too far.

(As for Intel product, please let the Unified Core thing turn out to not be hot garbage.)

 

[poke01]

(As for Intel product, please let the Unified Core thing turn out to not be hot garbage.)

it won't be

 

[DrMrLordX]

We don't know how much of it is the P-core being a bottleneck. Because Raptor Lake refresh on Intel 7 delivers the same peak perf as LNL/ARL

Keep in mind that Raptor Lake achieves this performance at generally higher clocks and power than Lunar Lake or Arrow Lake.

so either Intel 7 = N3B = 18A

No, even Intel 3 is a better overall performer on the v/f curve than Intel 7. Can Intel 3 handle the same max clocks as Intel 7? No idea, and we'll probably never find out. It's safe to say that Intel 4 can't which is a major reason why Intel never bothered using it with anything significant outside of Meteor Lake.

I do think that if Intel had chosen N3P for Panther Lake rather than 18a, we'd see a processor that performed better than Arrow/Lunar across the entire v/f curve AND that reached higher peak performance as well (e.g. that would not be limited to 5.1 GHz or lower), which is the main reason why I would say that 18a still can't equal N3P. Well, the main reason anyway. The differences between Lion and Cougar Cove are not (apparently) so great that Intel would be unable to reach target clocks on N3P Cougar Cove.

 

[511]

The efficiency figures (if the slides turn out to be accurate, of course) from PTL vs ARL/LNL on N3B make me think it's in the ballpark at least. The peak performance figures are another story but there's a caveat with that IMO: We don't know how much of it is the P-core being a bottleneck. Because Raptor Lake refresh on Intel 7 delivers the same peak perf as LNL/ARL so either Intel 7 = N3B = 18A or Intel's P core is hot garbage and can't scale anymore. And since Intel can't score clients yet sadly that P core is our only measure of peak performance but I don't think it's an accurate one. So pending more data I feel like putting 18A and N3P in the same basket is reasonable if efficiency figures are confirmed.

The problem is Intel 7 is a high clocking node... Like very high clocks

 

[511]

I do think that if Intel had chosen N3P for Panther Lake rather than 18a, we'd see a processor that performed better than Arrow/Lunar across the entire v/f curve AND that reached higher peak performance as well (e.g. that would not be limited to 5.1 GHz or lower), which is the main reason why I would say that 18a still can't equal N3P. Well, the main reason anyway. The differences between Lion and Cougar Cove are not (apparently) so great that Intel would be unable to reach target clocks on N3P Cougar Cove.

It would be costly and the difference would only be seen at higher end of V/F Curve at lowe end of the V/F curve 18A would be N3P or slightly better than it as you can see at lower end the curve.

 

[poke01]

It would be costly and the difference would only be seen at higher end of V/F Curve at lowe end of the V/F curve 18A would be N3P or slightly better than it as you can see at lower end the curve.
View attachment 133040

Why was N3E used for the GPU then?

 

[poke01]

Why was N3E used for the GPU then?

Now that I think about, it’s only used for the X SKU. So obviously it’s a premium sku.


Intel was pretty smart with Panther Lake SKUs and will maintain a good margin, they will sell well.

 

[511]

Why was N3E used for the GPU then?

Not optimized for GPU/SoC NVL iGPU will be 18AP and Xe3P

 

[511]

Intel was pretty smart with Panther Lake SKUs and will maintain a good margin, they will sell well.

The Layout is nice in itself if you look closely they can cut 8 Cores from the end and there is your 4+0+4 Tile

 

[Fjodor2001]

Looks almost the same as this:

 

[Joe NYC]

Looks almost the same as this:

View attachment 133054

Exactly where I dropped my kids off to school for 10+ years...

 

[Fjodor2001]

Exactly where I dropped my kids off to school for 10+ years...

So somewhere around E-Core St and P-Core Ave then.

 

[DavidC1]

IIRC Intel said FinFET did more for 22nm than any shrink itself did. It worked well in laptops I believe. And it lowered desktop TDP from 95W to 77W with a small clock increase. I don't see how more dies/wafer that use less power and give a small boost in performance is a "nothingburger".

It is a nothingburger, because it's desktops, and Sandy Bridge could be readily overclocked to beyond 4.5GHz a lot could do easily to 4.8GHz, while Ivy Bridge struggled to do 4.5. That's what a 37% transistor gain brought you. It was a decade of miserable gains since Sandy Bridge. Also a new process node doing 20% reduction is quite bad. My point is that using transistor performance as clock speed metric will get you wrong results.

Laptops weren't anything special either: https://www.notebookcheck.net/In-Review-Intel-Ivy-Bridge-Dual-Core-CPUs.75342.0.html

Clocks went up by a mere 100MHz, just like the desktop counterpart. It fell completely flat on its face compared to the world-changing product marketing it surrounded it. It was less significant than any other node previously, or even after it. It was a + level gain. Ivy Bridge was mostly the graphics brought on by the double density a node typically brings. Even graphics were overhyped. They called it Tick+, because of the graphics, but Clarkdale and Sandy Bridge had much bigger gains. Granted it was because it was starting at a low point, but again considering even Ivy Bridge graphics were shoddy, it was very misleading.

World-changing it was not. It barely even changed Intel. Even Silvermont, the product later explicitly attributed for the 37% gain, was eclipsed by Apple A6 in less than a month. I remember the AT article talking about the same thing, how the win was short lived. It probably killed any chance Intel thought they had of taking long-term mobile share.

 

[poke01]

was eclipsed by Apple A6 in less than a month

somethings still don't change even to this day...

 

[Geddagod]

It would be costly and the difference would only be seen at higher end of V/F Curve at lowe end of the V/F curve 18A would be N3P or slightly better than it as you can see at lower end the curve.
View attachment 133040

PTL supposedly has outright better SoC power than LNL, though the video they showed about the same
But N3P or slightly better doesn't really fit in with Intel also then making NVL 4+8 tiles TSMC N2/N2P too instead of 18A/18A-P.

 

[511]

PTL supposedly has outright better SoC power than LNL, though the video they showed about the same
But N3P or slightly better doesn't really fit in with Intel also then making NVL 4+8 tiles TSMC N2/N2P too instead of 18A/18A-P.

IDK why they moved tiles to TSMC I didn't make the decision lol but one of the stupidest decision...

 

[Tigerick]

IDK why they moved tiles to TSMC I didn't make the decision lol but one of the stupidest decision...

PPA and don't forget NPU6 tile which require more area and power. Do you have any idea which node is being used to make NPU6 tile?

 

[DavidC1]

PTL supposedly has outright better SoC power than LNL, though the video they showed about the same
But N3P or slightly better doesn't really fit in with Intel also then making NVL 4+8 tiles TSMC N2/N2P too instead of 18A/18A-P.

If we believe the Intel guy on reddit, Darkmont has 10% power efficiency optimization and the 18A process gives it additional 10%.

It's very possible at idle and mostly idle scenarios(Reading an article, with 1 tab), Lunarlake is still lower power, but if they can optimize the mostly idle to light load state, it'll still result in improvements for lot of cases.

Based on how well SteamOS was doing against Windows in low load battery life, Lunarlake's optimizations might not be as pronounced compared to predecessors, because it indicates that Linux doesn't have as many background applications firing up everything so often. Icelake might actually do quite well, because it had real low idle, it just didn't know how to keep it there.

 

[511]

PPA and don't forget NPU6 tile which require more area and power. Do you have any idea which node is being used to make NPU6 tile?

NPU6 Tile is on SOC so 18A the only node that is external in NVL IS N2
Take this tile remove the Core+L3 everything SoC is on 18A/AP the core+L3 is on N2/18AP

 

[Doug S]

If we believe the Intel guy on reddit, Darkmont has 10% power efficiency optimization and the 18A process gives it additional 10%.

That seems rather easy to believe given how much more headroom there is for improvement in E cores than P cores. Apple's E core improved IPC by 29% at the same power and only got the modest N3E->N3P bump. Apple's E cores occupy a lower rung on the power and performance spectrum than Intel's E cores so a 29% gain in one generation isn't going to happen for Darkmont, but a 10% gain seems reasonable if not perhaps slightly underwhelming.

 

[Josh128]

If we believe the Intel guy on reddit, Darkmont has 10% power efficiency optimization and the 18A process gives it additional 10%.

It's very possible at idle and mostly idle scenarios(Reading an article, with 1 tab), Lunarlake is still lower power, but if they can optimize the mostly idle to light load state, it'll still result in improvements for lot of cases.

Based on how well SteamOS was doing against Windows in low load battery life, Lunarlake's optimizations might not be as pronounced compared to predecessors, because it indicates that Linux doesn't have as many background applications firing up everything so often. Icelake might actually do quite well, because it had real low idle, it just didn't know how to keep it there.

Link to this Reddit guy's post please?

 

[DavidC1]

That seems rather easy to believe given how much more headroom there is for improvement in E cores than P cores. Apple's E core improved IPC by 29% at the same power and only got the modest N3E->N3P bump. Apple's E cores occupy a lower rung on the power and performance spectrum than Intel's E cores so a 29% gain in one generation isn't going to happen for Darkmont, but a 10% gain seems reasonable if not perhaps slightly underwhelming.

Their E cores are already better on that aspect, furthering my beliefs that they are the future.

 

[OneEng2]

Their E cores are already better on that aspect, furthering my beliefs that they are the future.

Are you then betting that things like SMT and AVX512 never happens in e-Cores?

How about higher clock speeds?

I have a theory that if you add everything needed to bring the performance of an E Core up to the level of a P core (or a Zen 6 core) you pretty much end up with a P core don't you?

Of course, moving forward, we need to start thinking about much more minor process improvements AND much longer times between them.

I am really interested to see how Intel's roadmap evolves now that they have decided that making money is an imperative.

 

[511]

That seems rather easy to believe given how much more headroom there is for improvement in E cores than P cores. Apple's E core improved IPC by 29% at the same power and only got the modest N3E->N3P bump. Apple's E cores occupy a lower rung on the power and performance spectrum than Intel's E cores so a 29% gain in one generation isn't going to happen for Darkmont, but a 10% gain seems reasonable if not perhaps slightly underwhelming.

They increased L2 by 50% from 4MB to 6MB ...