Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Tigerick]

x

8+16+4 mobile part? That's going to be interesting.

ARL-HX successor, NVL-HX

 

[Joe NYC]

it's 18AP a '+' and Intel's plus traditionally fixed frequency issues Intel has another problem that is TRUMP is seeing Intel as a way to save his name in history so that he is treated as a hero Intel has become a political playground as well among other stuff

You are taking the 3rd set of articles about Intel + TSMC combo way too seriously, after first 2 sets of articles about Intel negotiating with TSMC turn out to be complete fabrications by the press.

I don't see either side, Intel or TSMC seeing this type of investment of TSMC in Intel as desirable or advantageous for them. Which is a good tipoff that this is not going to be happening.

 

[gdansk]

You are taking the 3rd set of articles about Intel + TSMC combo way too seriously, after first 2 sets of articles about Intel negotiating with TSMC turn out to be complete fabrications by the press.

I don't see either side, Intel or TSMC seeing this type of investment of TSMC in Intel as desirable or advantageous for them. Which is a good tipoff that this is not going to be happening.

The problem is these types of stories where absolutely no one involved would benefit seem more believable when that buffoon injects himself.

The stock manipulators must love the plausibility any rumor can have now.

 

[511]

Hoho, I really hope you are not so naive about Intel roadmap. That past configuration might not valid: it might be combination of PTL and NVL:

	Node	CPU	GPU	NPU
PTL-H	Intel 18-A	4 + 4 + 4	10 Xe (N3E)	50
NVL-H	N2	4 + 8 + 4	12 Xe (N3E)	?
NVL-S Core Ultra 3	N2	4 + 8 + 4	2 Xe (Intel 3)
NVL-S Core Ultra 3 lower	Intel 18-A	4 + 0 + 4	2 Xe (Intel 3)

Why do you think Intel rather use cut die of N2 to create low cost Ultra3 if 18-A is OK. As I said, 18-A sucks...that's only logical explanation.

Remember I told you PTL will experience many hiccups: cutting 4 e cores are actually worse than MTL's CPU. At least MTL shipped with full die of 6+8. To me, PTL pretty much is DOA, so much for process leadership...

Please read the full thread on twitter before drawing conclusion

https://twitter.com/x/status/1924858617875808267

 

[511]

You are taking the 3rd set of articles about Intel + TSMC combo way too seriously, after first 2 sets of articles about Intel negotiating with TSMC turn out to be complete fabrications by the press.

I don't see either side, Intel or TSMC seeing this type of investment of TSMC in Intel as desirable or advantageous for them. Which is a good tipoff that this is not going to be happening.

i am not basing this on that i am basing on the fact that Trump don't like LBT cause he isn't letting them his way with Intel. I fully agree that Intel/TSMC JV is just a BS but not trump and Intel politics

 

[Tigerick]

Please read the full thread on twitter before drawing conclusion

https://twitter.com/x/status/1924858617875808267

View attachment 128503

Again where is 4+8+4 (18A) + 12? why use N2 to create 4+8+4 + 12?

And I believe in MLID: Intel will cut 4+8+4 (N2) to create Core Ultra 3. And do you still think Intel will use 18-A to create 4+8+4 as leaked by old roadmap?

You are clearly biased with Intel and you keep finding excuses for IFS without thinking logically. You thought Intel roadmap is solid even I said PTL-H is comparable to Gorgon Point. Do you really think PTL-H has any future? And you know what, you do not need to answer me because I know you will keep BS like Pat...

 

[511]

And I believe in MLID: Intel will cut 4+8+4 (N2) to create Core Ultra 3. And do you still think Intel will use 18-A to create 4+8+4 as leaked by old roadmap?

you meant NVL? cause the original twitter thread is Panther Lake. Let PTL launch and we will see

And I believe in MLID: Intel will cut 4+8+4 (N2) to create Core Ultra 3. And do you still think Intel will use 18-A to create 4+8+4 as leaked by old roadmap?

IDK about SKU but the plan to make 4+8 using 18AP is canned it is using TSMC N2 now

 

[Joe NYC]

The problem is these types of stories where absolutely no one involved would benefit seem more believable when that buffoon injects himself.

The stock manipulators must love the plausibility any rumor can have now.

Plausibility is in the eye of the beholder.

There is just something missing in the scenario described to make it plausible, which means it is not plausible.

Daniel Nenni on SemiWiki does not believe it for a second either. He did not believe the first 2 sets of stories either (which turned out to be fabrication).

Why would TSMC want to invest in stock of a failing competitor? When the same money could be used to strengthen TSMC in the extremely capital intensive business?

Not plausible to me (or to Daniel Nenni) but maybe plausible to people gullible to believe what they read from the press...

 

[gdansk]

Plausibility is in the eye of the beholder.

Yes.

Spoiler

I attribute to Trump malicious attempts to enrich himself or associates. That it would not benefit Intel, the United States, Taiwan or TSMC is irrelevant. And so no matter how detrimental it seems, it may be the administration's goal.

 

[Joe NYC]

i am not basing this on that i am basing on the fact that Trump don't like LBT cause he isn't letting them his way with Intel. I fully agree that Intel/TSMC JV is just a BS but not trump and Intel politics

You can take one rule straight to the bank: The dumbest thing is believing what press writes about Trump.

Putting money on what press writes - in case of 3 sets of articles about TSMC taking stake in Intel - would leave you leave you broke.

Intel jumped stock when the story first appeared, and days later tanked, when the story fizzled out. It just happened just this week, right in front of our eyes. Like clockwork.

 

[511]

You can take one rule straight to the bank: The dumbest thing is believing what press writes about Trump.

not the press lol i got this from someone else and like i have said TSMC Intel jv is bs

 

[Joe NYC]

not the press lol i got this from someone else

Are you talking about which die would come from which foundry (for Nova Lake) or the stories that TSMC would buy minority ownership in Intel?

 

[511]

Are you talking about which die would come from which foundry (for Nova Lake) or the stories that TSMC would buy minority ownership in Intel?

i am talking about the die thing lol not TSMC intel JV

 

[Geddagod]

IDK about SKU but the plan to make 4+8 using 18AP is canned it is using TSMC N2 now

Still so baffled by this. Is the 4+0 die even a full die, or is it a 4+8 18A die that is getting binned down?

 

[511]

Still so baffled by this. Is the 4+0 die even a full die, or is it a 4+8 18A die that is getting binned down?

it's a full die and i am same baffled as you are and it is a recent change after tan joined also it contains only 4P Cores doubt it will be even 20mm2 lol the HUB is 18A though in all SKUs

 

[Geddagod]

it's a full die and i am same baffled as you are and it is a recent change after tan joined also it contains only 4P Cores doubt it will be even 20mm2 lol the HUB is 18A though in all SKUs

I think >30mm2 tbh. But yea, super small either way.

 

[511]

I think >30mm2 tbh. But yea, super small either way.

It's 4P cores with like 8MB L3 lol and 2P cores share 4MB L2

 

[Josh128]

What a cluster f of SKUs, lol. Intel jumping though hoops and bending over backwards to both have the fastest and most efficient SKU possible and utilize 18A as much as possible to get at least some return on massive investment they've put into it. Its not looking good for the next few earnings reports, I'd guess...

 

[dangerman1337]

For NVL & RZL (400 and 500 series probably) probably having the same SKUs is it likely the lineup will look like this for Core Ultra 9, 7 and 5 on Desktop in terms of numbering?

• Core Ultra 9 - (4/5)95K.
• Core Ultra 9 - (4/5)85K.
• Core Ultra 7 - (4/5)75K.
• Core Ultra 7 - (4/5)65K.
• Core Ultra 5 - (4/5)55K.
• Core Ultra 5 - (4/5)45K.

I presume Core Ultra 9s will be dual Compute Tiles just like Ryzen 9 while 7 basically become the SKUs with one compute tile with full 8P core count. Unsure how bLLC will exactly fill i there because I bet those chonky 144MB tiles will have plenty of defective tiles. How TTL & HML will do SKUs w/ eLLC and if they'll do bLLC with eLLC again lol.

 

[reb0rn]

So you say AMD x3d on tsmc N2 will have huge defect rate also...

 

[DrMrLordX]

So you say AMD x3d on tsmc N2 will have huge defect rate also...

Why? There's no evidence of that.

 

[reb0rn]

because @dangerman1337 pointed issue with bLLC defect rate, its on same or very similar node, if AMD have no issue I see no intel problem here at all

 

[Josh128]

So you say AMD x3d on tsmc N2 will have huge defect rate also...

Its almost a given that the X3D cache die will NOT be using N2 in the first place, likely N4 or N3, but even if it was using N2, how do you arrive at that conclusion? N2 yields are supposedly already quite good and nothings launching for another 10-12 months or so.

 

[Josh128]

because @dangerman1337 pointed issue with bLLC defect rate, its on same or very similar node, if AMD have no issue I see no intel problem here at all

Intels bLLC is on the same die as its cores, AMDs is a separate cache only die. Yields will be much better for cache alone vs cache + compute together on one large die.

 

[511]

Intels bLLC is on the same die as its cores, AMDs is a separate cache only die. Yields will be much better for cache alone vs cache + compute together on one large die.

Hybrid bonding doesn't get 100% yields there must be some loss in yield during HB as well expect 95% yield during packing