Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[KompuKare]

For Zen6 ISA feature best I could find is this post

https://twitter.com/x/status/1870439328595214562

View attachment 114046

Nevermind software developers, anyone working on AVX/AMX at Intel/AMD/VIA needs to feature table big enough to cover a whole wall just to know what they themself support. Software developers have it even harder as that whole-wall table really needs to be 3D with a feature checkbox for each subset, each vendor and each vendors various CPUs.

Plenty of Schadenfreude to go around for Intel as their decades of segmentation is entirely on them. That plus their near endless fragmentation means Intel really have painted into a corner. A 3D or 4D corner, that is!

As for fragmentation and standards, well I feel the xkcd carton on standards is obligatory here (surprised nobody has posted it yet, actually):

Standards

xkcd.com

 

[alcoholbob]

View attachment 114045
CN source

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挺好,自证问题了~,电脑讨论(新),讨论区-生活与技术的讨论 ,Chiphell - 分享与交流用户体验

www.chiphell.com

It's a nice improvement, but even with all this it's still slower than a stock 14900K, considering some youtubers were running 4.3GHz ring with delided 285Ks, maxed tuned with direct die cooling and still couldn't beat a stock 14900K with same speed RAM. It's never going to catch up to the last gen. Just hope Intel doesn't fall even further behind before Nova Lake launches in 2027.

 

[SiliconFly]

.

 

[igor_kavinski]

Here’s what happens when you run an Intel Core Ultra 9 285K at 65W | Club386

Dialling down the wattage from 250W to 65W is an exercise well-suited to the cream of the Intel Arrow Lake CPU crop.

www.club386.com

 

[511]

Don't know if it was posted or not but Xe3 vs Xe1 in ARL-H is 2X the gains (12Xe3 vs 8e1) and we are looking at more than 100% performance

https://twitter.com/x/status/1873847774586020298

 

[dttprofessor]

Xe3 is FalconShore ?

 

[adroc_thurston]

Xe3 is FalconShore ?

More like Falcon Shores is an Xe3 derivative.

 

[poke01]

Don't know if it was posted or not but Xe3 vs Xe1 in ARL-H is 2X the gains (12Xe3 vs 8e1) and we are looking at more than 100% performance

https://twitter.com/x/status/1873847774586020298

Well its moving from 8Xe cores to 12Xe3 cores so 2X isnt't suprising.

 

[adroc_thurston]

Well its moving from 8Xe cores to 12Xe3 cores so 2X isnt't suprising.

It's actually impressive given that bandwidth doesn't grow on trees.

 

[poke01]

It's actually impressive given that bandwidth doesn't grow on trees.

Added 4 more cores, newer arch, higher clocks and is on N3E. PTL-H is going to be a great SoC for laptops.

 

[511]

Added 4 more cores, newer arch, higher clocks and is on N3E. PTL-H is going to be a great SoC for laptops.

also
> Beefed Up Chadmont
> No Tiling issues
> Good Low Power Island (not just meh)
Cons
> Meh P cores again afaik
> MoP missing not as low power vs LNL

My expectations
Also I don't know whether it will have PMIC support or not

 

[igor_kavinski]

Former Activision employee explaining APO: https://www.overclock.net/posts/29408511/

According to him, the answer to what APO does, is "complex".

 

[Philste]

It's actually impressive given that bandwidth doesn't grow on trees.

Because Intel for some reason still doesn't care and just puts enough cache in there to make it work even if it takes space. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.

 

[511]

Because Intel for some reason still doesn't care and just puts enough cache in there to make it work. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.

8 MB SLC is just not for the iGPU though it has many other uses

 

[adroc_thurston]

Also I don't know whether it will have PMIC support or not

it does not.

> Beefed Up Chadmont
> No Tiling issues
> Good Low Power Island (not just meh)

it's all goodenough already.

 

[511]

it does not.

I am not sure cause MTL-U has optional 2 PMIC Power Management I would not be surprised if PTL-U end up having this 2 PMICs are not costly w.r.t to BOM if we are allowed to diversify

it's all goodenough already.

Yeah hoping it matches M4 Pro (in MT ar least) and ST between M3/M4 that would make it damm good

 

[adroc_thurston]

MTL has optional 2 PMIC Power Management

stuff no one uses since MTL-M is a thing that did not really ship.

Yeah hoping it matches M4 Pro (in MT ar least) and ST

Well. Uh. 18A kinda gets in the way.

 

[511]

stuff no one uses since MTL-M is a thing that did not really ship.

I meant MTL-U😅

Well. Uh. 18A kinda gets in the way.

Nope it doesn't stop blaming it on 18A it's not even out yet we will wait for ARL-U performance to gauge 18A

 

[Hitman928]

I meant MTL-U😅

Nope it doesn't stop blaming it on 18A it's not even out yet we will wait for ARL-U performance to gauge 18A

Isn't ARL-U on Intel 3?

 

[511]

Isn't ARL-U on Intel 3?

Yes it is But we have a better comparison points with MTL-U -> ARL-U for the nodes (18A was supposed to be 15% faster than I3 so we would have our answer for 18A performance )

 

[Meteor Late]

That means believing Intel on the 15% of course.

 

[DavidC1]

Because Intel for some reason still doesn't care and just puts enough cache in there to make it work. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.

I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

> Beefed Up Chadmont
> Meh P cores again afaik

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.

 

[OneEng2]

I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.

I think the P Cores are most hamstrung by the ring bus latency ..... at least that is my theory .

 

[511]

I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.

We will see I have heard same improvements for both P and E of 5-8%

 

[DavidC1]

We will see I have heard same improvements for both P and E of 5-8%

You aren't getting more than 3-5% for Darkmont. Now for Arctic Wolf I anticipate a BIG upgrade.