Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Win2012R2]

I agree. APX is more interesting to me than AVX10

APX also requires recompile sadly, but it should be worth it for a lot more apps - JIT support will also benefit a lot of apps that get "recompiled" on start

 

[Thunder 57]

Please continue this if you want in an AMD thread, since so much of this is more AMD based than Intel based.

Fair enough. I edited my post to keep it more relevant.

 

[Hitman928]

Sure, but if AVX10 does not provide some of the AVX512 instructions then it does not make it a subset if at the same time it provides some stuff that isn't in AVX512 - they may intersect to a large degree, but being a subset is pretty much all in situation, that isn't the case here.

I haven't actually looked at all the supported instructions, but it's my understanding that the first iteration of AVX10 (IIRC this will now be 10.2 as 10.1 is being skipped) is just bringing most (but not all) of AVX512 to cores that don't support 512b wide instructions. There aren't any additional registers or instructions planned. It's not really a new AVX, it's a retrofit to allow for non-512b supporting cores to run AVX512 instructions.

 

[DrMrLordX]

Sorry if this has already been answered, but is there any particular reason why Intel can't support AVX-512 on all their cores using double-pumping tricks?

 

[desrever]

Sorry if this has already been answered, but is there any particular reason why Intel can't support AVX-512 on all their cores using double-pumping tricks?

Cause Intel has to do things the Intel way.

 

[DavidC1]

Sorry if this has already been answered, but is there any particular reason why Intel can't support AVX-512 on all their cores using double-pumping tricks?

It actually does cost fair bit of transistors/power for the extra registers even if it's double pumped,

 

[DrMrLordX]

It actually does cost fair bit of transistors/power for the extra registers even if it's double pumped,

How much area and extra power would they sacrifice vs something like AVX10?

 

[DavidC1]

How much area and extra power would they sacrifice vs something like AVX10?

The act of supporting 512-bit instructions is what adds to the cost. AVX10 won't change anything in that regard.

This is why I think they should have ended it at 256-bit and leave the rest to GPUs. Before the 10nm debacle Intel hinted at adding even more ridiculous 1024-bit support. Imagine the problems they would have had then!

 

[Win2012R2]

Before the 10nm debacle Intel hinted at adding even more ridiculous 1024-bit support

It's in AMX

And they are planning to add some AMX-AVX512 instructions, perhaps they are using those 1024 bit AMX registers

 

[511]

They are solving their OWN problem. AMD doesn't have the problem of AVX-512 not working on their E-cores. And if a point comes where AVX10.2 support gives a decent enough boost, AMD will have a CPU ready with support for it within 2 to 3 years. AMD hasn't been sitting still since 2016.

Make it 3-5 years 2 years is short

 

[511]

It's in AMX

And they are planning to add some AMX-AVX512 instructions, perhaps they are using those 1024 bit AMX registers

AMX is a MatMul Unit

https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2022-12/accelerate-ai-with-amx-sb.pdf

 

[DrMrLordX]

The act of supporting 512-bit instructions is what adds to the cost. AVX10 won't change anything in that regard.

So AVX10 is looking a bit pointless . . . ?

 

[Hitman928]

So AVX10 is looking a bit pointless . . . ?

It will allow Intel’s E-cores and hybrid CPUs access to some good AVX-512 instructions.

 

[511]

So AVX10 is looking a bit pointless . . . ?

Not really it will remove the biggest pain point with AVX Crap ( fragmentation and compatibility with instructions)

 

[DrMrLordX]

It will allow Intel’s E-cores and hybrid CPUs access to some good AVX-512 instructions.

Not really it will remove the biggest pain point with AVX Crap ( fragmentation and compatibility with instructions)

But they don't need AVX10 to do that. AMD supported AVX-512 in Zen4 just fine . . . except of course, as @desrever said, Intel gonna be Intel.

 

[511]

But they don't need AVX10 to do that. AMD supported AVX-512 in Zen4 just fine . . . except of course, as @desrever said, Intel gonna be Intel.

You know how fragmented AVX is they add an instruction in AVX it may be available in 256b only or we will have AVX-512 only implementation.

Intel can remove the features at will(VPintersect) with AVX10 a higher version is guaranteed to support lower version plus new feature and the will get rid of the crap you can only instruction at this width it will depend on data path supported on CPU the issue everyone pointed out is that of data path is 256b vs 512b on AMD

 

[Hitman928]

But they don't need AVX10 to do that. AMD supported AVX-512 in Zen4 just fine . . . except of course, as @desrever said, Intel gonna be Intel.

Yeah, they clearly don’t want to even do double pumped 512b support on the E-cores, so this is their path forward.

 

[511]

Yeah, they clearly don’t want to even do double pumped 512b support on the E-cores, so this is their path forward.

I guess until Unified Cores happen

 

[DrMrLordX]

Yeah, they clearly don’t want to even do double pumped 512b support on the E-cores, so this is their path forward.

That's just dumb.

You know how fragmented AVX is they add an instruction in AVX it may be available in 256b only or we will have AVX-512 only implementation.

Something that is feature-concurrent with Granite Rapids should support every instruction that anyone could ever want within the AVX/2/512 standard(s).

Intel can remove the features at will(VPintersect) with AVX10 a higher version is guaranteed to support lower version plus new feature and the will get rid of the crap you can only instruction at this width it will depend on data path supported on CPU the issue everyone pointed out is that of data path is 256b vs 512b on AMD

Removing features is exactly what they shouldn't be doing, since that leads to more fragmentation (albeit at the implementation level rather than the ISA level).

 

[511]

That's just dumb.

Intel being Intel as people have said

Something that is feature-concurrent with Granite Rapids should support every instruction that anyone could ever want within the AVX/2/512 standard(s).

yes but Granite Rapids supports the most latest ISA Featured Core and also it is the first Intel core to support AVX 10.1/512

Removing features is exactly what they shouldn't be doing, since that leads to more fragmentation (albeit at the implementation level rather than the ISA level).

I agree but the mess they have created with AVX 2/512 with AVX10 it is being sorted the last thing is data path that we all agree should be 512bits.

https://cdrdv2-public.intel.com/784343/356368-intel-avx10-tech-paper.pdf

 

[OneEng2]

I think they will agree on APX, which is genuinely useful stuff (more general purpose registers is always good), and AVX10 is likely to be Intel only in my view.

I don't know if anybody else noticed but Intel is now bastardising AMX too - on future SKUs they got something AMX-AVX512 ops, possibly supporting wide 1024 bit tiles they've got in AMX

APX for sure. I see no reason at all for AMD to support AVX10 since it will simply run on the 512b path in AND processors.

Sorry if this has already been answered, but is there any particular reason why Intel can't support AVX-512 on all their cores using double-pumping tricks?

Nope. Intel could have doubled pumped P cores and quad pumped E cores. From benchmarks OF Zen 4 vs Zen5, I think P cores will only be getting 70% the performance of full 522b registers, and E cores only about 40% (SWAG).

It actually does cost fair bit of transistors/power for the extra registers even if it's double pumped,

Only if you have the 512b path. Otherwise, I think it is minimal.

It will allow Intel’s E-cores and hybrid CPUs access to some good AVX-512 instructions.

Yes. AVX10 Gives Intel a good portion of the benefits of AVX512 without the big transistor budget penalty.


If AMD were to introduce a tiny core with only 128bit AVX data paths, I am sure they would adopt it too. I don't see them heading this direction though. Seems like they are designing for server and adapting to client while Intel appears to be doing the opposite.

 

[511]

APX for sure. I see no reason at all for AMD to support AVX10 since it will simply run on the 512b path in AND processors.

AMD will Adopt AVX10/512 bit just like they have done so far mimicking Intel

 

[gdansk]

mimicking Intel

🤔Won't Zen 6 ship before unified core? So they stand a good chance to be ahead of Intel again.

 

[511]

CN source

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[511]

🤔Won't Zen 6 ship before unified core? So they stand a good chance to be ahead of Intel again.

For Zen6 ISA feature best I could find is this post

https://twitter.com/x/status/1870439328595214562