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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

Senior member
Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15WIntel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7 360Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz4.8 GHz5 GHz4.8 GHz
L3 Cache12 MB6 MB12 MB12 MB
TDP15 - 55 W15 - 35 W17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5x-7467128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB48 GB32 GB128 GB
Bandwidth83 GB/s60 GB/s136 GB/s120 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz2.6 GHz2 GHz2.5 GHz
NPUGNA 3.017 TOPS48 TOPS49 TOPS






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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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For Zen6 ISA feature best I could find is this post
Nevermind software developers, anyone working on AVX/AMX at Intel/AMD/VIA needs to feature table big enough to cover a whole wall just to know what they themself support. Software developers have it even harder as that whole-wall table really needs to be 3D with a feature checkbox for each subset, each vendor and each vendors various CPUs.

Plenty of Schadenfreude to go around for Intel as their decades of segmentation is entirely on them. That plus their near endless fragmentation means Intel really have painted into a corner. A 3D or 4D corner, that is!

As for fragmentation and standards, well I feel the xkcd carton on standards is obligatory here (surprised nobody has posted it yet, actually):
8wZAvAJ.png
 
View attachment 114045
CN source

It's a nice improvement, but even with all this it's still slower than a stock 14900K, considering some youtubers were running 4.3GHz ring with delided 285Ks, maxed tuned with direct die cooling and still couldn't beat a stock 14900K with same speed RAM. It's never going to catch up to the last gen. Just hope Intel doesn't fall even further behind before Nova Lake launches in 2027.
 
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Added 4 more cores, newer arch, higher clocks and is on N3E. PTL-H is going to be a great SoC for laptops.
also
> Beefed Up Chadmont
> No Tiling issues
> Good Low Power Island (not just meh)
Cons
> Meh P cores again afaik
> MoP missing not as low power vs LNL

My expectations
Also I don't know whether it will have PMIC support or not
 
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It's actually impressive given that bandwidth doesn't grow on trees.
Because Intel for some reason still doesn't care and just puts enough cache in there to make it work even if it takes space. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.
 
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Because Intel for some reason still doesn't care and just puts enough cache in there to make it work. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.
8 MB SLC is just not for the iGPU though it has many other uses
 
Because Intel for some reason still doesn't care and just puts enough cache in there to make it work. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.
I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.
> Beefed Up Chadmont
> Meh P cores again afaik
3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.
 
I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.
I think the P Cores are most hamstrung by the ring bus latency ..... at least that is my theory 😉.
 
I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.
We will see I have heard same improvements for both P and E of 5-8%
 
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