Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[mikk]

Source? Just want to document this for future reference.

From here: https://www.computerbase.de/2024-06...024/#abschnitt_die_neuen_ecores_sind_der_star

Der Unterschied zwischen E-Cores an einem Ring mit LLC oder nicht liegt laut Intel aber nur bei rund 5 Prozent.

 

[Joe NYC]

Yeah, shame we can't do Z4c versus SKT isonode.

Zen 5c vs. SKT will be on same(ish) node.

 

[invisible_city]

Or how about a hypothetical 12 core Skymont only desktop CPU. Best option for non hybrid gaming CPU for more than 8 cores in one tile/die/ring? Or does the design of it prevent such a thing even if Skymont IPC really does achieve Golden Cove levels and high 4.XGHz clocks?

Or would real world performance not be that great with the deign by itself and not supplemented by the Lion Cove cores?

Or other weaknesses (latency???) such as latency of Skymont where it would not perform even clock normalized 4.6GHz close across 100% workloads as Golden Cove?

Or would real world performance at 4.6GHz clock normalized by on par across almost all apps as a hypothetical 4.6GHz all 12 P core 12th Gen GLC with HT disabled?

To be fair, having separate pmics per score/pcore cluster and with scheduling prioritised to ecores, lunar lake won’t take a major power efficiency hit from p-cores unless they are needed

 

[DavidC1]

I didn't, check the graphs at 8:35 and 9:40:

Skymont est. (MTL LPE + 38% INT +68% FP) = 1.90 INT 2.86 FP
Ultra 5 125H E 5.66 INT 6.44 FP @ 3.6GHz = 1.57 INT 1.79 FP
i9 14900K E 5.64 INT 6.01 FP @ 3.6GHz = 1.57 INT 1.67 FP
i5 13500H E 5.11 INT 5.79 FP @ 3.5GHz = 1.46 INT 1.65 FP
Ultra 5 125H LPE 3.44 INT 4.26 FP @ 2.5GHz = 1.38 INT 1.70 FP

People making the argument that because it's compared to an LPE core it'll trash in performance are making incorrect assumptions, when Intel themselves said there's 5% difference. Not only that, Lunarlake doesn't have a dedicated L3 cache to itself. It needs to share with many other entities and meant for power saving over performance.

There's also the fact that it's faster than Raptorlake when Sunny and Golden got 18% and 19% over Skylake, the supposed equivalence to Gracemont.

 

[Joe NYC]

LLC? Oh no the Strix Point people are gonna be mad at Microsoft again

We will see what the 32 MB LLC brings to Strix Halo

 

[DavidC1]

Lol, the recent events make me more convinced than ever that Eric Quinnell knows what he is talking about and uop caches are going the way of Hyperthreading.

Think about it. We had to back off from pipeline stages because adding stages is a guaranteed loss, while prediction is not.

Netburst architectures demonstrated that additional stages cost way more transistors than initially anticipated.

Since the process technologies keep getting better and better still, the idea is to cut the stages again:
-Which improves performance just by itself
-Simplifies design, thus less area and power use, thus more efficient
-Which allows for higher performance by using it elsewhere

Apple has the shortest pipeline at 9. It's that simple.

 

[invisible_city]

Lunar Lake E Cores are now able to talk to each other through their L1 cache, which should dramatically improve core - core latency: https://hothardware.com/reviews/intel-lunar-lake-deep-dive?page=3

Meaning we avoid this in Arrow Lake: https://www.anandtech.com/show/1704...hybrid-performance-brings-hybrid-complexity/6

Previously core communication required trip through ring bus, or in case of LP cores, Meteor Lake’s LP Scalable Fabric. See also https://chipsandcheese.com/2024/05/13/meteor-lakes-e-cores-crestmont-makes-incremental-progress/

Damned good design changes

 

[Saylick]

Lol, the recent events make me more convinced than ever that Eric Quinnell knows what he is talking about and uop caches are going the way of Hyperthreading.

Think about it. We had to back off from pipeline stages because adding stages is a guaranteed loss, while prediction is not.

Netburst architectures demonstrated that additional stages cost way more transistors than initially anticipated.

Since the process technologies keep getting better and better still, the idea is to cut the stages again:
-Which improves performance just by itself
-Simplifies design, thus less area and power use, thus more efficient
-Which allows for higher performance by using it elsewhere

Apple has the shortest pipeline at 9. It's that simple.

I'm guessing you're talking about this? https://vighneshiyer.com/misc/tesla-talk/Eric_Quinnell_Tesla_Talk.pdf

Interesting read.

 

[poke01]

Apple has the shortest pipeline at 9. It's that simple.

How many pipelines does Skymont have?

Edit: I found 14

 

[invisible_city]

I didn’t realize this but Skymont can be thought of as wider than Lion Cove (9 wide vs 8 wide, when the core can extract enough parallelism).

And has greater single threaded performance than Lion Cove, just can’t clock as high, and doesn’t scale with power as well. But we can fit 3 of them for every lion cove core. Exciting for a future that prioritizes threaded workloads.

 

[Hulk]

If we go by AMD and Intel's numbers, Arrow lake looks like it will lose single thread performance to Zen 5. I don't know why people care so much about the e-cores.

The E's have been somewhat helpful is you have apps that are highly multithreaded. They haven't been that strong from a compute point of view. That is all changed now. If Skymont lives up to Intel's hype we're talking about E cores that are Raptor Cove equivalents IPC-wise.

Lots of people have posted many times, "Just give us 12 P cores." Well how about 16 P cores, plus an additional 8 that are even stronger!

 

[invisible_city]

The E's have been somewhat helpful is you have apps that are highly multithreaded. They haven't been that strong from a compute point of view. That is all changed now. If Skymont lives up to Intel's hype we're talking about E cores that are Raptor Cove equivalents IPC-wise.

Lots of people have posted many times, "Just give us 12 P cores." Well how about 16 P cores, plus an additional 8 that are even stronger!

It actually has around 20% performance advantage at iso power.

Edit: and although intel’s graphs are non specific they indicate that the entire raptor cove power curve is shifted up

 

[Hulk]

Seriously? This thread is getting way ahead of itself. I thought I saw leaks that Zen 5 will have similar clocks, and dont forget ARL is giving up hyperthreading, so the E cores better be really good. ARL will still have to have a really good IPC increase for the P cores to beat Zen 5.

Perhaps, perhaps not.

Let's look at CB R23 MT. If Lion Cove is +15% over Raptor Cove and can do 5.4GHz nT and Skymont IS Raptor Cove IPC-wise and runs at 4.6GHz, then 8+16 ARL will do 48,000 points. That would be remarkable especially considering the lack of HT in Lion Cove. If Lion Cove in ARL get HT then we're looking at a score of 54,000 points.

We shall see if Intel has been fibbing with this recent information.

 

[Hulk]

I would suggest watching the High Yield video. Skymont looks like an absolute beast. It looks like you can still fit 3x Skymonts in the area of a single Lion Cove.

Shame that so much of the die is eaten up by this new NPU. I would have preferred to rather spend that die area on another 4 Skymonts and making the iGPU a bit bigger but the AI NPU wars cannot be stopped at this point.

When Intel starts spamming these new Skymonts (or future mont cores) in huge numbers, it should lead to some ridiculous MT performance and PPW.



LNL's implementation of LNC will not have HT but HT versions of LNC absolutely do exist. It isn't yet known if ARL has HT or not.

NPU-wars are so enticing for manufactures. The fruit is nice an low, easy to reach at this point in time. CPU fruit is much harder to reach.

 

[Hulk]

This generation x86 was kinda disappointing, eh?

Zen5 = 16% IPC, iso clock
LNL P-core = 14% IPC, clock regression (?)

How about Gracemont morphing into Raptor Cove? Did you forget about that?

 

[H433x0n]

This generation x86 was kinda disappointing, eh?

Zen5 = 16% IPC, iso clock
LNL P-core = 14% IPC, clock regression (?)

Zen 5 is not 16% IPC. Look at how they calculated that “16%” figure with some weird cherry picked Geekbench sub tests. If they used the same series of tests that they used on Lion Cove it would not net a 16% increase.

 

[invisible_city]

Zen 5 is not 16% IPC. Look at how they calculated that “16%” figure with some weird cherry picked Geekbench sub tests. If they used the same series of tests that they used on Lion Cove it would not net a 16% increase.

Also Intel stated that at iso power Lion Cove in Lunar Lame is up to an 18% performance uplift, not 14. Just depends on where you sit on the power curve.

Something most are missing is theyre describing 14% uplift in the Lunar Lake iteration, not in all implementations.

 

[poke01]

Lunar Lake E Cores are now able to talk to each other through their L1 cache, which should dramatically improve core - core latency: https://hothardware.com/reviews/intel-lunar-lake-deep-dive?page=3

Meaning we avoid this in Arrow Lake: https://www.anandtech.com/show/1704...hybrid-performance-brings-hybrid-complexity/6

Previously core communication required trip through ring bus, or in case of LP cores, Meteor Lake’s LP Scalable Fabric. See also https://chipsandcheese.com/2024/05/13/meteor-lakes-e-cores-crestmont-makes-incremental-progress/

Damned good design changes

Intel made some really good changes in client. CPU industry is in a good spot.

By the way anyone know the area of Skymont?

 

[H433x0n]

Also Intel stated that at iso power Lion Cove is up to an 18% performance uplift, not 14. Just depends on where you sit on the power curve. Theyre not juicing to the gills this time around so we get 14% in Lunar Lake.

Something most are missing is theyre describing 14% uplift in the Lunar Lake iteration.

Yeah, it’s entirely possible LNC in ARL-S ends up being 1-2% higher too with the added L2$.

The more I learn about Lion Cove the better it appears. It’s not as wide as expected, the ROB barely increased over Golden Cove. The power characteristics are significantly better over Golden Cove.

 

[Ghostsonplanets]

Another tidbit from Chips n' Cheese:

However, while the L2 can in theory do up to about 110B per cycle Intel has made the engineering choice on Lunar Lake to limit the L1 to L2 bandwidth to 64B per cycle for power and area savings.

So we're looking at possibilities of, on Arrow Lake DT:
- Bigger cache
- Return of HT
- L1 to L2 bandwidth to 110B per cycle

Intel new modern sea of cells design really allow for finer grained changes that fit different markers. Quite interesting.

 

[invisible_city]

Worth a watch, Intel Lunar Lake product manager describing the architectural choices:

They did the right thing: focused on exactly the power envelope they wanted, rather than trying to scale down an “everything” design

 

[Wolverine2349]

The E's have been somewhat helpful is you have apps that are highly multithreaded. They haven't been that strong from a compute point of view. That is all changed now. If Skymont lives up to Intel's hype we're talking about E cores that are Raptor Cove equivalents IPC-wise.

Lots of people have posted many times, "Just give us 12 P cores." Well how about 16 P cores, plus an additional 8 that are even stronger!

Or better yet Skymont only CPU disable the P cores and hten the dream of a 12 to 16 P core non hybrid Raptor Lake CPU is real. Well the clock speed, but if it can get to slightly above 5GHz and no caveats meaning it truly would perform across all work loads (excluding AVX512) as a hypothetical 12 to 16 P core clock normalized Raptor Lake HT disabled no caveats.

That way no scheduling hybrid gimmicks and you can get the 12-16 P Core Raptor Lake in Skymont by purchasing Arrow Lake disable Lion Cove cores and you got real Raptor Lake P cores. No HT but 12-16 cores HT would disabled.

Is this actually a real possibility or too good to be true.

 

[QuickyDuck]

On the bright side, with SRF intel can finally compete with 4th gen EPYC.
On the dark side, they are actually compete with 5th gen EPYC.

Still looking forward to skymont, hope they get ppa right.

 

[Henry swagger]

. Nice architecture detail video on skymont

 

[invisible_city]

I find the chadmont meme hilarious