Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[poke01]

you said you would make a Lunar Lake vs M3 thread sometime?

I’m waiting for the retail release silicon in laptops, it’s not fair to make tests with pre-release silicon.

 

[Ghostsonplanets]

Something about PTL and the future royal core:

https://www.reddit.com/r/intel/comments/1d88psj/some_funny_stories_regarding_the_current_pe_core

https://twitter.com/x/status/1798089713623970079

This matches what Exist has said for years, including that P Core tried to kill E core team and also others Cores projects at Intel. And that they were very adversarial against Jim Keller while the E core team was very helpful and accepted his guidance.

 

[DavidC1]

This matches what Exist has said for years, including that P Core tried to kill E core team and also others Cores projects at Intel. And that they were very adversarial against Jim Keller while the E core team was very helpful and accepted his guidance.

Being able to admit that you are wrong and accept guidance with a willing spirit is what makes society advance.

 

[FlameTail]

This matches what Exist has said for years, including that P Core tried to kill E core team and also others Cores projects at Intel. And that they were very adversarial against Jim Keller while the E core team was very helpful and accepted his guidance.

Interesting. I have some thoughts, but they best remain unspoken.

 

[Hulk]

That was made to achieve better efficiency. In Lunar Lake, E-cores are always active. Having more E cores will increase the idle power consumption. Intel is planning to turn off the whole P-cluster when it's not used.

Watching that video with the Intel engineers, they also say the P cores can be completely shut down and the CPU can run off the E's, and vice-versa.

 

[DavidC1]

I will predict the real highlight of the E core team will come with Arctic Wolf - the next big gain, with another 30% gain.

If the decline is to be expected, then it'll be after Arctic Wolf, just as Sandy Bridge was peak for IDC.

The fact that such a small core can perform that close to the P cores is a big suggestion that x64 cores have a long way to go. We will see if they manage to overcome ARM again.

 

[Ghostsonplanets]

Being able to admit that you are wrong and accept guidance with a willing spirit is what makes society advance.

Indeed.

Also, if Exist is right, Skymont is a direct result of Jim Keller pushing the E Core team. IIRC Keller pushed E Core team to make a core that maintain impressive PPA while aiming at matching or besting AMD Zen cores performance.

So the next E core might be a funny thing when compared to the P core (Perhaps the E core was the true Royal Core all along hahaha).

Question is if we'll see it on NVL or WCL.

 

[Hulk]

Can someone explain further the from the Intel engineers video?

Extended scalability - IP agnostic and partition agnostic

 

[SarahKerrigan]

Indeed.

Also, if Exist is right, Skymont is a direct result of Jim Keller pushing the E Core team. IIRC Keller pushed E Core team to make a core that maintain impressive PPA while aiming at matching or besting AMD Zen cores performance.

So the next E core might be a funny thing when compared to the P core (Perhaps the E core was the true Royal Core all along hahaha).

Question is if we'll see it on NVL or WCL.

The real Royal Core was the friends we made along the way.

 

[Ghostsonplanets]

Can someone explain further the from the Intel engineers video?

Extended scalability - IP agnostic and partition agnostic

Chips and Cheese had a very short but good explanation. Basically Intel P core team finally got rid of the old design methodology "Sea of fubs" that was more hand designed and specific for each node, which limited portability to other nodes, needing significant rework to be ported and that was very expensive and time consuming to make small changes.

Intel new approach for P cores is more usage of computer assisted design with usage of big cells, which allows them to make finer changes to their cores without being as so time consuming and also be more node agnostic, which means easier portability between different nodes/foundries.

 

[DavidC1]

I don't know where the hell the people are getting 4.5mm/1.5mm2 for Lion Cove/Skymont.

Taking the numbers from here:

https://twitter.com/x/status/1745244534978592784

And the schematic from here:

https://elchapuzasinformatico.com/wp-content/uploads/2024/04/Intel-Lunar-Lake-Dark-Silicon-Tile-Dummy.jpg

Lion Cove: 2.9-3mm2
Skymont: 0.95-1mm2

The E cores are 1mm2 again.

 

[FlameTail]

I will predict the real highlight of the E core team will come with Arctic Wolf - the next big gain, with another 30% gain.

If the decline is to be expected, then it'll be after Arctic Wolf, just as Sandy Bridge was peak for IDC.

What is Arctic Wolf? Darkmont successor?

The fact that such a small core can perform that close to the P cores is a big suggestion that x64 cores have a long way to go. We will see if they manage to overcome ARM again.

x86 needs wide, high-IPC cores that run at reasonable frequencies...

 

[DavidC1]

What is Arctic Wolf? Darkmont successor?

Yes, Darkmont is basically like Crestmont, previous generation's shrink.

Continuing on for Skymont,
The core is only bigger than the ARM's E cores. They are fraction of the size of modern ARM cores now.

2.2mm2 on A17 versus 1mm2 for Skymont on the same process technology. The Cortex cores on N4/N5 are in the 3mm2 range. Basically saying they aren't compact anymore. They are basically P cores level, that's why they perform like one. x86 vs ARM argument to be disapproved once again.

And again, people follow the crowd to erroneous conclusions rather than think for themselves. It's the people that make the difference, nothing else.

 

[yottabit]

Indeed.

Also, if Exist is right, Skymont is a direct result of Jim Keller pushing the E Core team. IIRC Keller pushed E Core team to make a core that maintain impressive PPA while aiming at matching or besting AMD Zen cores performance.

So the next E core might be a funny thing when compared to the P core (Perhaps the E core was the true Royal Core all along hahaha).

Question is if we'll see it on NVL or WCL.

So it sounds like we’re a generation or two away from wishing for an “Oops, all E core” edition when we just got done clamoring for an “Oops, all P core” model

How the turntables

 

[DavidC1]

It seems the P core is doing better relative to the competition. 3mm2 for Lion Cove on N3B is on par with 4.xmm2 for Zen 5 on N4. At least they got that right. Those are figures with L2 cache included.

The area difference used to be almost 2x.

 

[poke01]

Is panther lake mobile only?

 

[Wolverine2349]

So it sounds like we’re a generation or two away from wishing for an “Oops, all E core” edition when we just got done clamoring for an “Oops, all P core” model

How the turntables

I think that has more to do with not liking hybrid arch and scheduling quirks as the bashing of the e-cores and thus wanting an all P core edition cause P cores so much stronger,

And an all e-core edition even if not hybrid anymore its Gracemont which is just poor man's Skylake IPC with better Integer but much worse floating point and latency.

The sounds like we are wishing for an all e-core edition in a few generations is based on the assumption if (maybe big if or maybe not????) the e-cores can keep progressing the way they do, they will become the new P cores being smaller and more power efficient and the hybrid arch goes away.

After all the only reason Intel came up with the Big.Little P and e-cores is because the P cores were too big and not die space efficient due to their process node unlike AMD and TSMC where their P cores were smaller and they could fit more in a LGA 1700/1800/AM4/AM5 consumer sized socket.

Well now that the Intel Austin Atom core team appears to be advancing the e-cores to be like P cores and solve the problems of P cores being big, no Big.Little is/would necessary anymore. I doubt Intel ever makes Big.Little for desktop CPUs if the Austin Atom core team invested resources and was not stubborn in process node and refusing to use TSMC into making P cores smaller and more efficient just 3-4 years ago.

Well now they are or at least appear to be on our their to what it should have been 3-4 years ago and thus the path in which Big.Little would never have seen the desktop like it does not for AMD due to process node.

Intel if they did that 3-4 years ago, better off as we would have at least Zen 4 or maybe Zen 5 IPC level and clocks or higher but all strong smaller more than 8 power efficient cores on a single die/tile unlike the dual CCX/CCD dies and cross latency penalty beyond 4 cores with Zen 2 and beyond 8 cores with Zen 3 to present.

 

[inf64]

It seems the P core is doing better relative to the competition. 3mm2 for Lion Cove on N3B is on par with 4.xmm2 for Zen 5 on N4. At least they got that right. Those are figures with L2 cache included.

The area difference used to be almost 2x.

Zen 5 is around 3.46mm2

https://twitter.com/x/status/1797638258723365189

 

[DavidC1]

Zen 5 is around 3.46mm2

https://twitter.com/x/status/1797638258723365189

Not with the L2 cache included, which is the Strix Point shot, assuming 225mm2.

Even at 3.46mm2, they substantially closed the density gap compared to AMD using Lion Cove.

 

[lightisgood]

Zen 5 is around 3.46mm2

https://twitter.com/x/status/1797638258723365189

So, Pollack's law says that Zen 5 should achieve ~=12% IPC gain.
This means Zen 5 IPC may be inferior to Skymont IPC... OMG?

 

[DavidC1]

Also Intel stated that at iso power Lion Cove in Lunar Lame is up to an 18% performance uplift, not 14. Just depends on where you sit on the power curve.

Something most are missing is theyre describing 14% uplift in the Lunar Lake iteration, not in all implementations.

Lunar Lame? It is a huge advance in the power and system level department. Again, what are you smoking?

The power management advances and demonstrations back up Intel's claims of beating ARM/Apple on battery life!

 

[Hitman928]

Not with the L2 cache included, which is the Strix Point shot, assuming 225mm2.

Even at 3.46mm2, they substantially closed the density gap compared to AMD using Lion Cove.

Can you show the breakdown of your LNC estimate (visually)? I'm just eye balling it, but it looks bigger than 3 mm^2 to me. Maybe it's just my eyes though.

 

[DavidC1]

Can you show the breakdown of your LNC estimate (visually)? I'm just eye balling it, but it looks bigger than 3 mm^2 to me. Maybe it's just my eyes though.

I use paint and calculator? Exclude the L3 cache of course.

 

[Hitman928]

I use paint and calculator? Exclude the L3 cache of course.

Yeah, rough eyeballing it, I'm getting over 4 mm^2 (excluding L3). I'll use a graphics tool and see what I get.

 

[DavidC1]

Yeah, rough eyeballing it, I'm getting over 4 mm^2 (excluding L3). I'll use a graphics tool and see what I get.

It's 140mm2 for the die size.