Discussion Intel current and future Lakes & Rapids thread

[Hulk]

I know Intel 4 is ~ 7nm. Will they have a product that is ~3-4nm or are they jumping to Intel 20, which I believe is supposed to equate to ~2nm?

With all of the process issues Intel has had since 14nm you've got to admit they squeeze every last bit of performance out of a process once they sink their teeth into it.

Just look at Rocket Lake, the best an last Intel 14nm silicon vs. Raptor Lake in it's latest iteration on Intel 7.

I agree it makes for an awkward lineup and branding, but Intel's only alternative would be to launch 14th gen and 15th gen desktop simultaneously, which would be confusing in its own right. My bet is we'll see 14th gen launch as a combo of MTL mobile parts and RPL refreshes for filler, and then 15th gen as LNL (premium mobile), ARL (mobile and higher end desktop), and MTL (low end desktop).

I like this but have a slightly different take.

Yes, 14th gen will be Raptor Refresh on the desktop and Meteor Lake mobile.

But then I predict that Intel (as usual) will fall in love with the yields that are finally occurring with Intel 4 and 15th generation in 2025 will be a Meteor Lake Refresh that include better, lower voltage mobile parts as well as high clock speed desktop parts.
Of course this course would mean that AMD has given them enough rope to slow down.
If Zen 5 appears as promised then there will be some scrambling at Intel and those results are always hard to predict!

 

[jpiniero]

I know Intel 4 is ~ 4nm. Will they have a product that is ~3nm or are they jumping to Intel 20, which I believe is supposed to equate to ~2nm?

AFAIK Meteor Lake's CPU tile is the only product intended for I4 and Granite Rapids's CPU tile is the only product on I3, assuming Sierra Forrest is cancelled.

 

[Hulk]

AFAIK Meteor Lake's CPU tile is the only product intended for I4 and Granite Rapids's CPU tile is the only product on I3, assuming Sierra Forrest is cancelled.

I meant to type Intel 4 is ~7nm and is there anything between that and Intel 20 planned? Seems like a big jump.

 

[Geddagod]

I meant to type Intel 4 is ~7nm and is there anything between that and Intel 20 planned? Seems like a big jump.

To start of with, TSMC doesn't disclose HCC SRAM density
Intel 7/Intel 10nm is ~7nm.
Intel 10nm HD is ~ 7nm
Intel 7 HP ~ TSMC 7nm
Intel 7 is roughly 15% larger than TSMC 7nm HDC cells

Intel 4 is between 3nm and 5nm HP density
Intel 4 is between 7 and 5nm HDC density

But design/routing is also important...
Ironically enough, both zen 3 (7nm) and zen 4 (5nm) have worse 512KB L2 data array density than their respective competitors, GLC (Intel 7) and RWC (Intel 4).
And the entire core for RWC vs entire core for Zen 4, without L2 or L3, is ~30% larger.
So if Intel 4 is ~TSMC 7nm, redwood cove must be the best design the Intel team has ever had in terms of perf/transistor (edit: perf/transistor not perf/area, I'm dum lol) , or it's a significant IPC regression

 

[Geddagod]

Ok, I understand your position, I just don't agree with it but that's ok.

One point though is that you keep saying that 10nm SF density increased, but this is not true from the explanation in the Anandtech article. Density is transistors per area. So density went down, it's just that they could use fewer, higher performing transistors which more than made up for the decreased density to allow for lower area.

No, them using fewer, higher performing transistors is an assumption you made. Which IDEK if you could do that, if you could use fewer HP cells vs more HD cells for the same performance, because overall what the critical path needs is frequency, and even more HD cells are still going to have the same or lower frequency cap as less HD cells, since I don't think frequency is limited by stuff like too few transistors (if anything I would think having less transistors is better for high frequency).
What was officially stated was the number of buffers between the transistors was able to decrease in a cell. So actually, they were able to pack more transistors per^2 mm because the amount of space between each transistor was able to go down, even if the size of each individual transistor grew. And for a reduction in buffers to allow for an overall increase in density, either we all have been seriously underestimating the importance of buffers for overall density, or (and what I think is more likely) is that overall transistor size shrunk by such a small amount that the decrease in buffer size was able to overall increase density.
And regardless of density increasing or decreasing for 10nm SF, I mentioned the different dimensions for 10nm SF vs OG 10nm even before debating or being asked about the effect of the individual transistor growing larger, so it wasn't like I wasn't aware or trying to mislead people about the effects of the SF change before hand.

 

[Geddagod]

I know Intel 4 is ~ 7nm. Will they have a product that is ~3-4nm or are they jumping to Intel 20, which I believe is supposed to equate to ~2nm?

With all of the process issues Intel has had since 14nm you've got to admit they squeeze every last bit of performance out of a process once they sink their teeth into it.

Just look at Rocket Lake, the best an last Intel 14nm silicon vs. Raptor Lake in it's latest iteration on Intel 7.


I like this but have a slightly different take.

Yes, 14th gen will be Raptor Refresh on the desktop and Meteor Lake mobile.

But then I predict that Intel (as usual) will fall in love with the yields that are finally occurring with Intel 4 and 15th generation in 2025 will be a Meteor Lake Refresh that include better, lower voltage mobile parts as well as high clock speed desktop parts.
Of course this course would mean that AMD has given them enough rope to slow down.
If Zen 5 appears as promised then there will be some scrambling at Intel and those results are always hard to predict!

I don't think the problem is Intel falling in love with the yields/frequencies, I think it's just Intel unable to hit the desired yields/frequencies needed for a desktop launch.
Before 10nm, IIRC, Intel released new desktop generations with ~frequencies and ~IPC even, but on a new node.

 

[Geddagod]

I agree it makes for an awkward lineup and branding, but Intel's only alternative would be to launch 14th gen and 15th gen desktop simultaneously, which would be confusing in its own right. My bet is we'll see 14th gen launch as a combo of MTL mobile parts and RPL refreshes for filler, and then 15th gen as LNL (premium mobile), ARL (mobile and higher end desktop), and MTL (low end desktop).

You would have to wonder what the difference between the I9 and I5 skus are going to be then, if ARL is i7 and i9, and MTL is i5 and below.
ARL should bring a new arch, so ~15% IPC, and since it's on TSMC 3nm, I doubt Fmax is going to be any worse than the ~ 5.5GHz on MTL.
The gap between the MT of skus being large is something we have seen before, but the ST gap potentially being that large might present a huge problem for consumers.
Ig you could artificially (or who knows maybe LNC clocks super badly) limit clock speed for ARL i7s to only get ST marginally higher than MTL i5s, but that would be a marketing nightmare since the clock speeds of the i7 would have to be lower than the clock speeds for the i5 for only marginally more overall ST performance (since the IPC difference should be pretty large).
Or you could just sell i5s and above as ARL, but that doesn't really make sense with the whole 'high volume products on internal/cheaper nodes' paradigm since i5s are way higher volume compared to the i7s and i9s I believe.

 

[Geddagod]

That's not crucial, Intel's biggest problem is the again new Desktop cpu socket in 2024. This is already absurd, and in the end Intel will sink the deepest it has ever been.

Ig people just don't appreciate irony anymore haha

 

[Geddagod]

Anyone know why Harukaze on twitter deleted this? It certainly looks legit.
Also 500 watts on GNR vs 600 watts on Turin?
What's the difference between Intel and AMD TDP again?

 

[nicalandia]

Well....

https://twitter.com/x/status/1637485463597457408

 

[Markfw]

Well....
View attachment 78399

https://twitter.com/x/status/1637485463597457408

How can you even run at stock ? And Zen 4 threadripper ? will rip this one to shreds. This is insane power usage. and the custom water loop and it reaches 95c in 6 seconds at only 4.7 ghz ???? How can they even sell these ???? And 1039 watts thats at only 1.13 vcore ??

 

[Geddagod]

How can you even run at stock ? And Zen 4 threadripper ? will rip this one to shreds. This is insane power usage. and the custom water loop and it reaches 95c in 6 seconds at only 4.7 ghz ???? How can they even sell these ???? And 1039 watts thats at only 1.13 vcore ??

Markfw not bringing up Genoa every single time someone talks about SPR challenge (impossible)

 

[nicalandia]

How can you even run at stock ? And Zen 4 threadripper ? will rip this one to shreds. This is insane power usage. and the custom water loop and it reaches 95c in 6 seconds at only 4.7 ghz ???? How can they even sell these ???? And 1039 watts thats at only 1.13 vcore ??

At stock it only does 64,000 points and 420 Watts, there is really no need for Zen4 based ThreadRippers, Those Xeons have Zen2 3990X performance levels at stock and on Water Cooler when OC.

 

[Hitman928]

No, them using fewer, higher performing transistors is an assumption you made. Which IDEK if you could do that, if you could use fewer HP cells vs more HD cells for the same performance, because overall what the critical path needs is frequency, and even more HD cells are still going to have the same or lower frequency cap as less HD cells, since I don't think frequency is limited by stuff like too few transistors (if anything I would think having less transistors is better for high frequency).
What was officially stated was the number of buffers between the transistors was able to decrease in a cell. So actually, they were able to pack more transistors per^2 mm because the amount of space between each transistor was able to go down, even if the size of each individual transistor grew. And for a reduction in buffers to allow for an overall increase in density, either we all have been seriously underestimating the importance of buffers for overall density, or (and what I think is more likely) is that overall transistor size shrunk by such a small amount that the decrease in buffer size was able to overall increase density.
And regardless of density increasing or decreasing for 10nm SF, I mentioned the different dimensions for 10nm SF vs OG 10nm even before debating or being asked about the effect of the individual transistor growing larger, so it wasn't like I wasn't aware or trying to mislead people about the effects of the SF change before hand.

It's not an assumption I made, it's literally in the quote from Anandtech. Buffers are made up of transistors, so by increasing transistor spacing and removing buffers you are decreasing density. I'm not sure why this is hard to understand. Overall area can still decrease with decreased density because you are using less transistors. Buffers are only needed if your transistor can't drive the next stage at desired frequencies. Using higher performing transistors can mitigate the need for buffers.

 

[IntelUser2000]

I know Intel 4 is ~ 7nm. Will they have a product that is ~3-4nm or are they jumping to Intel 20, which I believe is supposed to equate to ~2nm?

Didn't we go through this before?

Intel 4 is 7nm, and 20A is likely what was originally the 5nm process. 2nm by original definition is still 2 generations away from 20A, and remember 18A is kinda like a plus.

Why would 20A be an accurate indication of a process when Intel 4(which uses the same name convention) doesn't?

 

[Geddagod]

It's not an assumption I made, it's literally in the quote from Anandtech. Buffers are made up of transistors, so by increasing transistor spacing and removing buffers you are decreasing density. I'm not sure why this is hard to understand. Overall area can still decrease with decreased density because you are using less transistors. Buffers are only needed if your transistor can't drive the next stage at desired frequencies. Using higher performing transistors can mitigate the need for buffers.

Didn't know buffers were also made of transistors. Thought they were referring to literarily just the physical spacing.
But if overall area still decreases, but the amount of transistors overall also decreases, how can you know if density overall increased or decreased if you don't know the exact amount of the transistors and area decreased?
Also less related but on the HCC SRAM cells, Intel 7 has higher density than Intel 10nm so the idea that Intel is relaxing density of the individual cells in order to get better yields doesn't look to be true.

 

[Hitman928]

Didn't know buffers were also made of transistors. Thought they were referring to literarily just the physical spacing.
But if overall area still decreases, but the amount of transistors overall also decreases, how can you know if density overall increased or decreased if you don't know the exact amount of the transistors and area decreased?

Because you are increasing the gate pitch (i.e., increasing transistor to transistor spacing) while at the same time removing transistors per cell. There is only one way for density to go in such a situation and that is down.

Also less related but on the HCC SRAM cells, Intel 7 has higher density than Intel 10nm so the idea that Intel is relaxing density of the individual cells in order to get better yields doesn't look to be true.

Where is this analysis coming from?

 

[Geddagod]

Because you are increasing the gate pitch (i.e., increasing transistor to transistor spacing) while at the same time removing transistors per cell. There is only one way for density to go in such a situation and that is down.



Where is this analysis coming from?

Not if you are also decreasing area, which again, there is no numerical amount.
A scenario to show case this:
100 transistors in 10 mm^2, 50 of them are buffers , 10 transistors per mm^2
80 transistors in 8 mm^2, 30 of them are buffers, 10 transistors per mm^2
Density is number of transistors and area.

As for numbers for HCC SRAM density, from Mark Bohr, redfire on twitter.

 

[Hulk]

Didn't we go through this before?

Intel 4 is 7nm, and 20A is likely what was originally the 5nm process. 2nm by original definition is still 2 generations away from 20A, and remember 18A is kinda like a plus.

Why would 20A be an accurate indication of a process when Intel 4(which uses the same name convention) doesn't?

Okay yes. For some reason I was under the incorrect assumption that while Intel 4 is ~7nm I thought that Intel 20 would be referring closer to reality and be ~2nm. But as you pointed out they naming structure is going to remain accurate only in that small "Intel" numbers are essentially smaller nodes but the same have no mathematical meaning except in relation to other "Intel x" named nodes.
Got it. Thanks.

This new naming structure allows them to better align with TMSC node "sizes" and allows them to get away from the dreaded "+" syndrome. ie Intel 20A+ will not exist and actually be Intel 18A.

So let me rephrase my original question. Are the following the only nodes we currently know Intel has on the horizon?

Intel 7
Intel 4
Intel 20A
Intel 18A

 

[Geddagod]

Okay yes. For some reason I was under the incorrect assumption that while Intel 4 is ~7nm I thought that Intel 20 would be referring closer to reality and be ~2nm. But as you pointed out they naming structure is going to remain accurate only in that small "Intel" numbers are essentially smaller nodes but the same have no mathematical meaning except in relation to other "Intel x" named nodes.
Got it. Thanks.

This new naming structure allows them to better align with TMSC node "sizes" and allows them to get away from the dreaded "+" syndrome. ie Intel 20A+ will not exist and actually be Intel 18A.

So let me rephrase my original question. Are the following the only nodes we currently know Intel has on the horizon?

Intel 7
Intel 4
Intel 20A
Intel 18A

I think Intel made some throwaway phrase about Intel 16A. No idea if I'm just making this up or actually remember it however haha.

 

[Geddagod]

Because you are increasing the gate pitch (i.e., increasing transistor to transistor spacing) while at the same time removing transistors per cell. There is only one way for density to go in such a situation and that is down.



Where is this analysis coming from?

It also looks like, according to this Intel employee, Intel 10SF shrunk down the fin height from 54 to 53nm as well as other minor tweaks and optimizations.

 

[Hitman928]

Not if you are also decreasing area, which again, there is no numerical amount.
A scenario to show case this:
100 transistors in 10 mm^2, 50 of them are buffers , 10 transistors per mm^2
80 transistors in 8 mm^2, 30 of them are buffers, 10 transistors per mm^2
Density is number of transistors and area.

As for numbers for HCC SRAM density, from Mark Bohr, redfire on twitter.

In your example the transistor/gate pitch didn't change which is not what happened. You have to adjust for the increased gate pitch.

It also looks like, according to this Intel employee, Intel 10SF shrunk down the fin height from 54 to 53nm as well as other minor tweaks and optimizations.

Fin height is in the vertical and is not taken into account when discussing transistor area or density.

I don't know how to explain it any clearer so I won't continue on any more with this conversation. Believe what you want to believe, we'll see if Intel can keep to their promises with their next few nodes.

 

[Geddagod]

In your example the transistor/gate pitch didn't change which is not what happened. You have to adjust for the increased gate pitch.



Fin height is in the vertical and is not taken into account when discussing transistor area or density.

I don't know how to explain it any clearer so I won't continue on any more with this conversation. Believe what you want to believe, we'll see if Intel can keep to their promises with their next few nodes.

The decreased number of total transistors was the the indication of increased gate pitch.
However since area also decreased, the effect on density which is #transistors and area is unknown.
You're right, I was wrong about 10nm SF increasing density, I thought that the buffers weren't transistors.
However you aren't right about 10SF being a decrease in density, since there is literarily no way to show that since we don't know how much the area decreased as well as the number of transistors.

 

[Hitman928]

The decreased number of total transistors was the the indication of increased gate pitch.
However since area also decreased, the effect on density which is #transistors and area is unknown.
You're right, I was wrong about 10nm SF increasing density, I thought that the buffers weren't transistors.
However you aren't right about 10SF being a decrease in density, since there is literarily no way to show that since we don't know how much the area decreased as well as the number of transistors.

Actually adjust for the increased gate pitch and you’ll have your answer.

 

[Geddagod]

Actually adjust for the increased gate pitch and you’ll have your answer.

But overall area also decreased, along with the number of transistors. The growth of the gate pitch might have been minor, or could have been major, but overall if the % increase in area decreasing outpaced the %# transistor, density would grow. The effect is unknown. Intel 10SF had changes beyond just gate pitch, as shown by that Intel engineer.

Also, if you want anymore proof of Intel 10nm+ or Intel 10nm SF not "hitting targets" or not being equivalent to a TSMC 7nm node beyond just the OG Intel 10nm
We can look at actual products too:
Icelake density per mm^2 was ~50MTr/mm^2 on 10nm+
Which is also around the density of Zen 2 and Zen 3 CCDs.
SPR is closer to ~30, but also has chonky caches, uses way more HP cells, etc etc