Discussion Intel current and future Lakes & Rapids thread

[IntelUser2000]

Abused at 4GHz you mean. Above 3.2GHz the E cores are actually less efficient than the P cores. For Zen cores the dynamic range doesn't seem to be too high to cover all bases Intel still isn't able to.

That is totally different from a low power island dedicated to power management. It's a completely different scale. Repeating myself, Nehalem has 486 class core just for that. Sure the LP core on Meteorlake is far more capable, but it's going to be something like Crestmont at 1GHz on a low frequency, ultra low leakage design and SoC process.

So instead finally moving the PCH into the compute block making it a true SoC they invent yet another core level? Doesn't sound like positive progress to me.

Again, an ultra low power core just for power management. The PCH already has some microcontroller for various duties such as power management. You don't see it because it's transparent.

Not doing a true SoC has Intel-specific reasons I outlined before in addition to the whole industry moving to the chiplet/tile arrangement. Also they can use a process better tailored to SoC tile. Remember they are using HP Intel 4 tiles with higher performance but higher leakage current and power.

 

[Exist50]

Meteor lake is p-core is 15-20 better than raptor cove.. arrow lake is aiming for 45% plus greater than alder lake for p-core performance 😏

TLDW? Hope he isn't claiming those as IPC numbers.

That is totally different from a low power island dedicated to power management

These would be proper, OS-visible cores, not just for running power management firmware.

 

[IntelUser2000]

These would be proper, OS-visible cores, not just for running power management firmware.

Yea but comparing P vs E and extrapolating that to LP is wrong is what I am saying. The E cores are on the HP process because it's on the same die.

Also it's natural progression as the block grows it goes from having a simple microcontroller to a complex one then to a full on CPU core.

 

[Exist50]

Yea but comparing P vs E and extrapolating that to LP is wrong is what I am saying. The E cores are on the HP process because it's on the same die.

Ok. There's a balance to be struck, however. Make the SoC cores too weak (and 1GHz is too weak), and you need to constantly be turning on the compute tile for performance reasons. Push them too hard, and the process choice, voltage rail, etc turn against you.

 

[IntelUser2000]

Ok. There's a balance to be struck, however. Make the SoC cores too weak (and 1GHz is too weak), and you need to constantly be turning on the compute tile for performance reasons. Push them too hard, and the process choice, voltage rail, etc turn against you.

Notebookcheck review shows one Tigerlake Inspiron reaching 0.65W for CPU package power. Alderlake model gets 2W. My XPS 12 Ivy Bridge is 2-2.5W* so they regressed back to pre-Haswell levels for the CPU power!

Every 1W on a package level is greater than 1W on a system level because the CPU can't go low until the other parts of the system shuts down.

*Actually I had to work it to get it that low. I had to shut down most processes and search for the latest drivers and even do some registry edits. Otherwise it wouldn't go below 3W. It also takes 2-3 mins to get it to 2W. 3W is the realistic package power average, 2W is the absolute minimum, and 2.5W is the idle power that can be reached in few seconds.

@Exist50 I don't know if your "lack of confidence" is due to what your sources are alluding to. Because being able to do *everything* except above a very light load should do amazing things to improve the above scenario I described. With a small load then the compute block kicks in at low frequencies and take over. Nevermind not being able to reach low enough idle like with Alderlake, even if you could like Tigerlake it takes dozens of seconds and minutes to reach the lowest idle even if you stop all activity immediately.

I am talking about things like state transitions for the peripheral functions. Such as the storage controller, keyboard backlighting, webcam, touchpad, and display controller, USB, and WiFi.

Even if Tigerlake can reach 0.5W CPU package power, you can't reduce that further because C state power is pretty much all leakage power, and it's still doing minute compute to handle all the peripheral functions powering down meaning the frequency you reach 0.5W is extremely slim very close to zero. An SoC optimized process cutting leakage power by multitudes, and a CPU block powerful enough to do everything the regular cores would do for C state transitions should do lots of good. 1GHz Crestmont is orders of magnitude better than microcontrollers.

It doesn't have to handle light work loads because what if 1GHz is enough to reach CPU package idle in 1 second rather than the dozens of seconds and even minutes to reach now? Or even if it still takes a long time it would do at 1W package power average rather than 3W? 1GHz is about the LFM frequency of the CPU cores anyway. You are talking Crestmont which is likely Sunny Cove class or even Zen 3.

@moinmoin Meteorlake and future uses Foveros which allows extremely close proximity between the cores so it'll cut down both on interconnect power use and response time over on package solution they use now for the mobile chips. Yes it's slower than on-die but it's closer to on-die than it's off-die and a compromise of multitude of factors plus you can optimize each tiles for a specific function like bringing SoC to be low leakage and compute high performance rather than middling both having it on-die.

Both yours and @Exist50 point all relies on execution of the said ideas. Because while Lakefield had all the potential for very low power x86 platform it did nothing. The hybrid part didn't seem to work either as the performance was poorer than Jasper Lake even in single thread at the same power.

 

[Exist50]

Notebookcheck review shows one Tigerlake Inspiron reaching 0.65W for CPU package power. Alderlake model gets 2W. My XPS 12 Ivy Bridge is 2-2.5W* so they regressed back to pre-Haswell levels for the CPU power!

Every 1W on a package level is greater than 1W on a system level because the CPU can't go low until the other parts of the system shuts down.

*Actually I had to work it to get it that low. I had to shut down most processes and search for the latest drivers and even do some registry edits. Otherwise it wouldn't go below 3W. It also takes 2-3 mins to get it to 2W. 3W is the realistic package power average, 2W is the absolute minimum, and 2.5W is the idle power that can be reached in few seconds.

@Exist50 I don't know if your "lack of confidence" is due to what your sources are alluding to. Because being able to do *everything* except above a very light load should do amazing things to improve the above scenario I described. With a small load then the compute block kicks in at low frequencies and take over. Nevermind not being able to reach low enough idle like with Alderlake, even if you could like Tigerlake it takes dozens of seconds and minutes to reach the lowest idle even if you stop all activity immediately.

I am talking about things like state transitions for the peripheral functions. Such as the storage controller, keyboard backlighting, webcam, touchpad, and display controller, USB, and WiFi.

Even if Tigerlake can reach 0.5W CPU package power, you can't reduce that further because C state power is pretty much all leakage power, and it's still doing minute compute to handle all the peripheral functions powering down meaning the frequency you reach 0.5W is extremely slim very close to zero. An SoC optimized process cutting leakage power by multitudes, and a CPU block powerful enough to do everything the regular cores would do for C state transitions should do lots of good. 1GHz Crestmont is orders of magnitude better than microcontrollers.

It doesn't have to handle light work loads because what if 1GHz is enough to reach CPU package idle in 1 second rather than the dozens of seconds and even minutes to reach now? Or even if it still takes a long time it would do at 1W package power average rather than 3W? 1GHz is about the LFM frequency of the CPU cores anyway. You are talking Crestmont which is likely Sunny Cove class or even Zen 3.

Ok, my understanding is that the SoC Atoms exist for somewhat more demanding tasks. Like, can you scroll through a webpage without using the compute tile? Can you type a document? Etc. I think the first incarnation of it will be quite rough around the edges, but I'm optimistic long term.

It's worth noting that the same team that's doing Meteor Lake did Tiger Lake and Broxton before that. So I think that they can at least recover from Alder Lake, but I'm worried about how much some of Meteor Lake's poor design choices might drag it down. N6 is a very good process, though, so here's hoping.

 

[IntelUser2000]

Ok, my understanding is that the SoC Atoms exist for somewhat more demanding tasks. Like, can you scroll through a webpage without using the compute tile? Can you type a document? Etc. I think the first incarnation of it will be quite rough around the edges, but I'm optimistic long term.

They seem to have a performance-at-all-costs mindset which seems to be a barrier in reaching the mobile market.

If they are doing what you are suggesting then I have less confidence as the frequency needed might be quite high and that's going to ripple into overall decision making process. So rather than lowest leakage as with 1GHz suggestion they will need to use a higher leakage design.

With Kabylake Y and all the beyond normal optimizations one guy said during Youtube playback CPU package power was under 1.2W. This means on a laptop with 11 inch screen you are talking 20 hours of battery life. The default setting on even brand new laptops go nowhere near this because they want to bundle all the software and notifications and startup applications. Those settings cut the battery life in half, sometimes to 40%.

Of course you need post-Haswell to reach that low preferrably post-Broadwell. I ignore pre-Haswell used laptops for that reason. Best is Kabylake but mostly for Youtube's VP9 support. Beyond that who cares?

 

[Doug S]

I remember hearing that they had a small team experimentally porting either Golden Cove or Redwood Cove to TSMC (unsure which node), but I think they canceled the exercise. Seems like they're currently porting Lion Cove to Intel 3, N3, and 20A all for release within a year or so, so do they really have resources to spare?

That may be a marketing exercise hoping to show that Intel 3 / 20A is better than N3. Yeah Intel doing the part would not be "impartial" like if was Qualcomm, but this is for marketing not serious benchmarking.

 

[coercitiv]

Ok, my understanding is that the SoC Atoms exist for somewhat more demanding tasks. Like, can you scroll through a webpage without using the compute tile? Can you type a document? Etc. I think the first incarnation of it will be quite rough around the edges, but I'm optimistic long term.

I was hoping they would keep this for system idle and/or connected standby, using it for light loads smells like latency to me.

I don't understand Intel anymore, on one side they push over 25W+ through a mobile chip for a simple ST workload, on the other side (if what you say is true) they want to improve battery life by adding even more layers of complexity in thread management. It's almost as if nobody in there believes in incremental and reliable improvements anymore, all they want is the revolutionary change that puts them back on top.

 

[biostud]

Who will do the packaging of meteor lake, Intel or TSMC?

 

[DrMrLordX]

I remember hearing that they had a small team experimentally porting either Golden Cove or Redwood Cove to TSMC (unsure which node), but I think they canceled the exercise. Seems like they're currently porting Lion Cove to Intel 3, N3, and 20A all for release within a year or so, so do they really have resources to spare?

Heck if I know. They've had so much turnover and so many product delays that it's impossible to know their capabilities anymore.

“purposefully”

Hey we all know Intel hit their target with the 10nm launch in 2017, right? That was totally above board.

Who will do the packaging of meteor lake, Intel or TSMC?

Presumably Intel.

 

[moinmoin]

They seem to have a performance-at-all-costs mindset which seems to be a barrier in reaching the mobile market.

I guess that's really the main problem I have with Intel. They still launch plenty designs mobile first or even mobile only, but the designs themselves are anything but mobile oriented anymore.

I don't understand Intel anymore, on one side they push over 25W+ through a mobile chip for a simple ST workload, on the other side (if what you say is true) they want to improve battery life by adding even more layers of complexity in thread management. It's almost as if nobody in there believes in incremental and reliable improvements anymore, all they want is the revolutionary change that puts them back on top.

Couldn't have put it better. There just doesn't seem to be an overarching roadmap at Intel, just a lot of area specific "quick" solutions that add up in overall complexity.

 

[nicalandia]

If there will be LP E Cores on the SOC this means that Intel has ported Gracemont Cores to TSMC. That will make a future Compute Tile by TSMC quite feasible.

 

[repoman27]

N6 is a very good process, though, so here's hoping.

Why do you believe Intel will use an n-2 process family for the SoC tile rather than n-1? Wouldn't N5P or N4 make a lot more sense for this product?

 

[jpiniero]

Why do you believe Intel will use an n-2 process family for the SoC tile rather than n-1? Wouldn't N5P or N4 make a lot more sense for this product?

SoC probally doesn't scale as well as you think, esp compared to the wafer prices. Intel might still use N4 because that's what TSMC gave them.

 

[repoman27]

SoC probally doesn't scale as well as you think, esp compared to the wafer prices. Intel might still use N4 because that's what TSMC gave them.

N4 vs. N6 = 38% logic area reduction, 27% SRAM area reduction, +9% speed at ISO power or -29% power at ISO speed.

Even if analog doesn't scale at all, why would you not take the area and power reductions of N4 where you could, especially considering this is a Foveros design?

 

[IntelUser2000]

I was hoping they would keep this for system idle and/or connected standby, using it for light loads smells like latency to me.

I hope it really works the way they want it to be if what @Exist50 is saying is what they are going for.

You potentially might end up with the same scenario down the road because you need to keep beefing up those cores to stay ahead of application demands even for light load tasks. Why not for C-state transitions only?

N4 vs. N6 = 38% logic area reduction, 27% SRAM area reduction, +9% speed at ISO power or -29% power at ISO speed.

Even if analog doesn't scale at all, why would you not take the area and power reductions of N4 where you could, especially considering this is a Foveros design?

It's probably significantly cheaper? Meteorlake will end up representing something like 50%+ of Intel's shipments. The lower cost Core i3-style have ultra high volumes and is traditionally reserved for 100mm2 die chips.

 

[nicalandia]

More Sapphire Rapids SKUs disclosed by YuuKi_AnS

 

[nicalandia]

From: Yuuki_AnS @ yuuki_ans

◇ Xeon Platinum 8400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 8490H 60-core / 120-thread 1.90-2.90GHz TDP350W 8480
　 + 56-core / 112-thread 2.00-3.00GHz TDP350W
　 8471N 52-core / 104-thread 1.80-2.80GHz TDP300W
　 8470Q 52-core / 104-thread 2.00-3.00GHz TDP350W
　 8470N 52-core / 104-thread 1.70-2.70GHz TDP300W
　 8470 52-core / 104-thread 2.00-3.00GHz TDP350W 8468V
　 48- core / 96-thread 2.40-2.90GHz TDP330W
　 8468H 48-core / 96-thread 2.10-3.00GHz TDP330W
　 8468 48-core / 96-thread 2.10-3.00GHz TDP350W
　 8461V 48-core / 96-thread 2.20-2.80GHz TDP300W
　 8460Y + 40-core / 80-thread 2.00-2.80GHz TDP300W
　 8460H 40-core / 80-thread 2.20-3.10GHz TDP350W
　 8458P 44-core / 88-thread 2.70-3.20GHz TDP350W
　 8454H 32-core / 64-thread 2.10-2.70GHz TDP270W
　 8452Y 36-core / 72-thread 2.00-2.80GHz TDP300W
　 8450H 28-core / 56-thread 2.00-2.60GHz TDP250W
　 8444H 16-core / 32-thread 2.00-2.80 GHz TDP320W

◇ Xeon Gold 6400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 6454Y + 32-core / 64-thread 2.60-3.80GHz TDP270W
　 6454S 32-core / 64-thread 2.20-2.80GHz TDP270W
　 6448Y 32-core /64-thread 2.20-3.30GHz TDP225W
　 6448H 32-core / 64-thread 2.20-3.82GHz TDP225W
　 6444Y 16-core / 32-thread 3.50-4.10GHz TDP270W
　 6442Y 24-core / 48-thread 2.60-3.00GHz TDP225W
　 6441V 44 -core / 88-thread 2.10-2.60GHz TDP270W
　 6438Y + 32-core / 64-thread 1.90-2.10-3.00GHz TDP205W
　 6438N 32-core / 64-thread 2.00-3.00GHz TDP205W
　 6438M 32-core / 64-thread 2.30-3.10GHz TDP205W
　 6434H 8-core / 16-thread 4.00-4.10GHz TDP205W
　 6434 8-core / 16-thread 3.90-4.20GHz TDP270W
　 6430 32-core / 64-thread 1.90-3.00 GHz TDP270W
　 6428N 32-core / 64-thread 1.80-2.70GHz TDP185W
　 6426Y 16-core / 32-thread 2.60-3.50GHz TDP185W
　 6421N 32-core / 64-thread 1.80-2.70GHz TDP185W
　 6418H 24-core / 48-thread 2.00 -3.00GHz TDP185W
　 6416H 18-core / 36-thread 2.20-3.00GHz TDP165W
　 6414U 32-core / 64-thread 2.00-2.60GHz TDP250W

◇ Xeon Gold 5400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 5420+ 28-core / 56-thread 1.90-2.10GHz TDP205W
　 5418Y 24-core / 48-thread 2.10-2.90GHz TDP185W
　 5418N 24-core / 48-thread 2.00-2.80GHz TDP165W
　 5416S 16-core / 32-thread 2.10-2.90GHz TDP150W
　 5415+ 8-core / 16-thread 2.90-3.70GHz TDP150W
　 5411N 24-core / 48-thread 2.00-2.80GHz TDP165W

◇ Xeon Silver 4400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 4416+ 20-core / 40-thread 2.10-3.00GHz TDP165W
　 4410T 12-core / 24-thread 2.10-3.00GHz TDP145W
　 4410T 10-core / 20-thread 2.90-3.10GHz TDP150W

◇ Xeon Bronze 3400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 3408U 8-core / 16-thread 1.80-1.90GHz TDP125W



EDit.

Coming up this week... Sapphire Rapids vs Genoa courtesy of Yuuki_AnS @ yuuki_ans , this is going to be a QS sample SPR. Early samples of SPR did not fare well against Milan so let's hope the QS samples fair better this time.

 

[Exist50]

They seem to have a performance-at-all-costs mindset which seems to be a barrier in reaching the mobile market.

I don't understand Intel anymore, on one side they push over 25W+ through a mobile chip for a simple ST workload, on the other side (if what you say is true) they want to improve battery life by adding even more layers of complexity in thread management. It's almost as if nobody in there believes in incremental and reliable improvements anymore, all they want is the revolutionary change that puts them back on top.

Couldn't have put it better. There just doesn't seem to be an overarching roadmap at Intel, just a lot of area specific "quick" solutions that add up in overall complexity.

I think part of the problem is that there are many teams within Intel, each with their own (sometimes quite distinct) culture, and very little high-level coordination between them. When they have to come together to create an actual product, this is where inefficiencies will start cropping up.

For example, I've been told that the Israeli team (C2DG, IDC, whatever you want to call them) cares first and foremost about peak performance, power and everything else be darned. Basically, in their heart of hearts, they just want to make a fast desktop chip. Since the big core team is part of this org, that's why you see 10s of watts consumed for a single thread. Additionally, Intel's process design has historically come from the feedback of the big core team, and so that mindset has influenced even the manufacturing side.

The US team (DDG, Oregon for SoC, mostly Austin TX for Atom) is much more power aware from their time spent in the Broxton days, and also more modern and agile about design methodology. But they've gotten an unfortunate assortment of products over the years, and have been struggling with attrition and boneheaded top-down choices for MTL.

Jim Keller supposedly tried to orchestrate things a bit during this time there. He elevated Atom as a first-class citizen, forcing its inclusion into the product roadmap, brought in Royal as a hedge/counter to the dominance of the big core, etc. But from what I've heard, his interactions with the Israeli team were more adversarial than cooperative, both causing and resulting in his actions to balance their power within the company.

Anyway, when you put all this together, combined with a heavy dose of "Not Invented Here" Syndrome (even within the company), that's how you get the contradictions in the product line. Socket changes every two years, feature mismatches between cores, wonkiness with power consumption, etc. Curious to see if/how it stabilizes going forward.

Also, as a disclaimer, most of this feedback comes from the US side, so probably is biased or inaccurate to some degree. Can't vouch for it personally, but figured I'd share.

 

[Exist50]

Why do you believe Intel will use an n-2 process family for the SoC tile rather than n-1? Wouldn't N5P or N4 make a lot more sense for this product?

Meteor Lake was originally supposed to be a '22 product. There's what, ~100mm2 of silicon between the SoC and IO dies? Even if you assume decent scaling (which is not necessarily a given), would TSMC even have the capacity to spare? And then how much would that balloon costs? Plus, N6 is a great process that tons of people are working with. Low leakage, high performance, tons of IP available, etc. N4 might still be the better choice from a PnP standpoint, but N6 makes a lot of sense from a logistical standpoint.

 

[Exist50]

From: Yuuki_AnS @ yuuki_ans

◇ Xeon Platinum 8400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 8490H 60-core / 120-thread 1.90-2.90GHz TDP350W 8480
　 + 56-core / 112-thread 2.00-3.00GHz TDP350W
　 8471N 52-core / 104-thread 1.80-2.80GHz TDP300W
　 8470Q 52-core / 104-thread 2.00-3.00GHz TDP350W
　 8470N 52-core / 104-thread 1.70-2.70GHz TDP300W
　 8470 52-core / 104-thread 2.00-3.00GHz TDP350W 8468V
　 48- core / 96-thread 2.40-2.90GHz TDP330W
　 8468H 48-core / 96-thread 2.10-3.00GHz TDP330W
　 8468 48-core / 96-thread 2.10-3.00GHz TDP350W
　 8461V 48-core / 96-thread 2.20-2.80GHz TDP300W
　 8460Y + 40-core / 80-thread 2.00-2.80GHz TDP300W
　 8460H 40-core / 80-thread 2.20-3.10GHz TDP350W
　 8458P 44-core / 88-thread 2.70-3.20GHz TDP350W
　 8454H 32-core / 64-thread 2.10-2.70GHz TDP270W
　 8452Y 36-core / 72-thread 2.00-2.80GHz TDP300W
　 8450H 28-core / 56-thread 2.00-2.60GHz TDP250W
　 8444H 16-core / 32-thread 2.00-2.80 GHz TDP320W

◇ Xeon Gold 6400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 6454Y + 32-core / 64-thread 2.60-3.80GHz TDP270W
　 6454S 32-core / 64-thread 2.20-2.80GHz TDP270W
　 6448Y 32-core /64-thread 2.20-3.30GHz TDP225W
　 6448H 32-core / 64-thread 2.20-3.82GHz TDP225W
　 6444Y 16-core / 32-thread 3.50-4.10GHz TDP270W
　 6442Y 24-core / 48-thread 2.60-3.00GHz TDP225W
　 6441V 44 -core / 88-thread 2.10-2.60GHz TDP270W
　 6438Y + 32-core / 64-thread 1.90-2.10-3.00GHz TDP205W
　 6438N 32-core / 64-thread 2.00-3.00GHz TDP205W
　 6438M 32-core / 64-thread 2.30-3.10GHz TDP205W
　 6434H 8-core / 16-thread 4.00-4.10GHz TDP205W
　 6434 8-core / 16-thread 3.90-4.20GHz TDP270W
　 6430 32-core / 64-thread 1.90-3.00 GHz TDP270W
　 6428N 32-core / 64-thread 1.80-2.70GHz TDP185W
　 6426Y 16-core / 32-thread 2.60-3.50GHz TDP185W
　 6421N 32-core / 64-thread 1.80-2.70GHz TDP185W
　 6418H 24-core / 48-thread 2.00 -3.00GHz TDP185W
　 6416H 18-core / 36-thread 2.20-3.00GHz TDP165W
　 6414U 32-core / 64-thread 2.00-2.60GHz TDP250W

◇ Xeon Gold 5400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 5420+ 28-core / 56-thread 1.90-2.10GHz TDP205W
　 5418Y 24-core / 48-thread 2.10-2.90GHz TDP185W
　 5418N 24-core / 48-thread 2.00-2.80GHz TDP165W
　 5416S 16-core / 32-thread 2.10-2.90GHz TDP150W
　 5415+ 8-core / 16-thread 2.90-3.70GHz TDP150W
　 5411N 24-core / 48-thread 2.00-2.80GHz TDP165W

◇ Xeon Silver 4400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 4416+ 20-core / 40-thread 2.10-3.00GHz TDP165W
　 4410T 12-core / 24-thread 2.10-3.00GHz TDP145W
　 4410T 10-core / 20-thread 2.90-3.10GHz TDP150W

◇ Xeon Bronze 3400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
　 3408U 8-core / 16-thread 1.80-1.90GHz TDP125W



EDit.

Coming up this week... Sapphire Rapids vs Genoa courtesy of Yuuki_AnS @ yuuki_ans , this is going to be a QS sample SPR. Early samples of SPR did not fare well against Milan so let's hope the QS samples fair better this time.

View attachment 64261

Looking at those SKUs, seems like the 32c Gold and below might be prime candidates for the elusive monolithic MCC die. Certainly it doesn't make sense to sell multiple 8c SKUs cut all the way down from 60.

But yeah, SPR vs Genoa is going to be a blood bath. Though it'll be interesting to see by how much.

 

[jpiniero]

Looking at those SKUs, seems like the 32c Gold and below might be prime candidates for the elusive monolithic MCC die. Certainly it doesn't make sense to sell multiple 8c SKUs cut all the way down from 60.

It does when yields are that bad.

As I've mentioned before, a 32 core monolithic part would be well over 700 mm2.

 

[Exist50]

It does when yields are that bad.

We've seen nothing to suggest that yields are that bad, and even if they were, all the more reason to have another die option. But this would be cutting down 13/15 cores per die. You don't see anything even close to that with Alder Lake.

 

[jpiniero]

We've seen nothing to suggest that yields are that bad, and even if they were, all the more reason to have another die option. But this would be cutting down 13/15 cores per die. You don't see anything even close to that with Alder Lake.

S goes down to 2+0. U/P goes down to 1+4. Can't go much further than that.