Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

Looking at those SKUs, seems like the 32c Gold and below might be prime candidates for the elusive monolithic MCC die. Certainly it doesn't make sense to sell multiple 8c SKUs cut all the way down from 60.

According to Yuuki_AnS the MCC Monolithic die(Translated to English)

Source: https://northwood.blog.fc2.com/blog-entry-11438.html

"It is said that "Sapphire Rapids-SP" has an XCC consisting of 15-core x 4 dies and an MCC die called a monolithic die. Products made from XCC dies will probably have multiples of 4 cores, so anything that doesn't apply is likely to be made from MCC dies ... but most are multiples of 4 cores. There are only two types of numbers, not multiple cores of 4, Xeon Silver 4110T for 10-core / 20-thread and Xeon Gold 6116U for 18-core / 36-thread. Assuming that there is no metamorphosis specification created with 2 dies of XCC, these two types are likely to be derived from MCC dies.

So how many cores are there in the MCC die? Although it can be expected to be 18-core or higher, there seems to be a view of 24-core and a view of 32-core at the moment. In terms of "Sapphire Rapids-X" for workstations / HEDT, up to 56-core / 112-thread for Expert Workstation, which is said to be based on XCC dies, and Mainstream Workstation for MCC dies. Is up to 24-core / 48-thread.


Perhaps the MCC die is 28-core (when it is released for Mainstream Workstation, it will be expanded to 24-core to improve the yield?) ."


What is my Take?(nicalandia)

I believe anything lower than 24C/48T is prime candidate for Monolithic and it does not need to be multiple of 4 to make it strictly a XCC. 8, 16, 24 CORES could be made on a single MCC.

But yeah, SPR vs Genoa is going to be a blood bath. Though it'll be interesting to see by how much.

Let's hope the QS samples with proper Speeds performs better than the early ES samples.

Lets keep an eye on Yuuki_Ans

https://twitter.com/yuuki_ans

 

[Exist50]

So how many cores are there in the MCC die? Although it can be expected to be 18-core or higher, there seems to be a view of 24-core and a view of 32-core at the moment. In terms of "Sapphire Rapids-X" for workstations / HEDT, up to 56-core / 112-thread for Expert Workstation, which is said to be based on XCC dies, and Mainstream Workstation for MCC dies. Is up to 24-core / 48-thread.

Perhaps the MCC die is 28-core (when it is released for Mainstream Workstation, it will be expanded to 24-core to improve the yield?) ."


What is my Take?(nicalandia)

I believe anything lower than 24C/48T is prime candidate for Monolithic and it does not need to be multiple of 4 to make it strictly a XCC. 8, 16, 24 CORES could be made on a single MCC.

There are a lot of 32c SKUs on the Gold 6400 list, and the Gold SKUs will probably be among the best sellers. I don't think this is a coincidence, and imo, it strongly implies the existence of either a native 32c die, or even something with a couple of extra cores for yield. But we'll see. If such a product exists, hopefully it comes to the HEDT market as well, if not the XCC one.

Let's hope the QS samples with proper Speeds performs better than the early ES samples.

Well QS should be basically final, so exempting any anomalies regarding the test platform, we should actually be able to get useful data. My 2 cents is that it'll probably end up competitive with Milan, but certainly not Genoa.

 

[pakotlar]

Really.... They have lied so many times about so many things, that I have no idea what they did due to stupidity, and how many times it was on purpose.

Does it matter ?????

Yes, it does. Their roadmap has been consistent, and as we get closer to release, they reiterate those timeframes, suggesting either they are confident in them or are deceiving shareholders. It is not the latter. The evidence to the contrary is MLID, a far less reliable source.

 

[pakotlar]

Meteor Lake was originally supposed to be a '22 product. There's what, ~100mm2 of silicon between the SoC and IO dies? Even if you assume decent scaling (which is not necessarily a given), would TSMC even have the capacity to spare? And then how much would that balloon costs? Plus, N6 is a great process that tons of people are working with. Low leakage, high performance, tons of IP available, etc. N4 might still be the better choice from a PnP standpoint, but N6 makes a lot of sense from a logistical standpoint.

Where did you see Meteor Lake as a ‘22 product?
The first announcement from Intel has it as a ‘23 product.

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[Exist50]

Where did you see Meteor Lake as a ‘22 product?

That's what it was originally planned as. And even if you want to talk about official communications, when Intel said that their first 7nm/Intel 4 products were delayed by 6 months (announced at the same time the process delay was)...that's Meteor Lake. Looking more like a year delay at this point.

 

[pakotlar]

That's what it was originally planned as. And even if you want to talk about official communications, when Intel said that their first 7nm/Intel 4 products were delayed by 6 months (announced at the same time the process delay was)...that's Meteor Lake. Looking more like a year delay at this point.

Intel never announced Meteor Lake as a ‘22 product, full stop. The delays in manufacturing process under Bob Swan’s tenure are fairly outdated at this point. No delays under Gelsinger in the CPU or foundry space that I’m aware of.

 

[jpiniero]

No delays under Gelsinger in the CPU or foundry space that I’m aware of.

The last official communication was that Sapphire was going to launch in 1H. That obviously didn't happen.

It also seems like they are going to delay 7 nm by another year. They just haven't admitted it yet.

 

[lobz]

Intel never announced Meteor Lake as a ‘22 product, full stop. The delays in manufacturing process under Bob Swan’s tenure are fairly outdated at this point. No delays under Gelsinger in the CPU or foundry space that I’m aware of.

you are living in a dream world

 

[Markfw]

you are living in a dream world

So far he has called like 3 or 4 different members, liars, including me for pointing out the obvious, Intel being late on promises. I will just wait until he gives up, or too many members point out his flaws for him to keep being in denial.

Probably won't happen.

 

[repoman27]

Meteor Lake was originally supposed to be a '22 product. There's what, ~100mm2 of silicon between the SoC and IO dies? Even if you assume decent scaling (which is not necessarily a given), would TSMC even have the capacity to spare? And then how much would that balloon costs? Plus, N6 is a great process that tons of people are working with. Low leakage, high performance, tons of IP available, etc. N4 might still be the better choice from a PnP standpoint, but N6 makes a lot of sense from a logistical standpoint.

Yeah, the SoC and IOE tiles together are 105 mm². The total for all of the active tiles is only 166 mm² though, compared to ~206 mm² of Intel 7 for ADL 2+8+2 LP plus another 54 mm² of 14nm for PCH-P. Honestly, I think the SoC tile would be considerably larger if it were N6. Also, I'm trying to rationalize Intel's design decisions with this statement:

They basically told management, "If you want us to compete with Apple, we need to be on the best process, like they are" and looking towards the original mid-2022 production timeframe, that was N3.

Apple went with a 148 mm² monolithic SoC on N5P for the M2. Maybe Intel was reluctant to do a monolithic design on TSMC N3, and it is certainly true that if they can't find a volume product to manufacture on Intel 4, they will have to abandon being a leading edge foundry. They also want to prove that they are ahead in packaging so they hype Meteor Lake as "Foveros", even though it's just a standard 2.5D package with a passive silicon interposer.

But is N6 any cheaper or demonstrably better than Intel 7 for the SoC and IOE tiles? Maybe the TSMC N5 nodes are all jammed up, but it seems like Intel 7 might be as well. Did Intel figure that they would be supply constrained due to SPR and RPL? If Intel wasn't planning on a split strategy all along, with an Intel 7 monolithic die family to be marketed contemporaneously with Meteor Lake, then why wouldn't they have used Intel 7 for the SoC and IOE tiles?

 

[Exist50]

Apple went with a 148 mm² monolithic SoC on N5P for the M2. Maybe Intel was reluctant to do a monolithic design on TSMC N3

Just for context, around 2019, the assumption for pretty much everyone was that N3 would be ready for volume production around mid-2022, and would show up in the A16. But Intel wasn't the only one who slipped timelines, and also, N3's kinda been a mess even ignoring the delay. uzzi38 has commented on that before as well, but talk to literally anyone who's so much as evaluated it. Been a right pain.

But is N6 any cheaper or demonstrably better than Intel 7 for the SoC and IOE tiles?

So here's my understanding of things. Keller really didn't like being tied to Intel foundry for several reasons, one of which was the lack of availability of ecosystem IP. I.e. if Intel wanted any hard IP on the process (e.g. PCIe PHYs), they had to do it themselves. So a trial of sorts was arranged. The desktop Alder Lake PCH would be manufactured on Samsung 14nm, not Intel, as a way for Intel's design teams to dip their toes into external manufacturing. Yes, the desktop Alder Lake chipset is manufactured by Samsung. Well it turns out that the chipset team loved it. They were super impressed with the ease of use and quality + availability of IP.

So looking at Meteor Lake, they knew that not only could it be done, but they were very confident in their ability to reduce their overall workload (by buying IP if needed), as well as avoiding some of the process churn and issues they encountered with Intel's fabs. IIRC, the entire MTL SoC die ends up funneled through the chipset team at some point, though I'm hazy on the details. And that aside, I'm pretty sure N6 is also significantly better from a technical standpoint, looking at low-mid voltage performance and especially leakage vs Intel 7. Might even be cheaper, but the economics of that are hard to know for obvious reasons. Seriously, N6 is the hammer for every nail.

 

[DrMrLordX]

this is going to be a QS sample SPR.

Allegedly Intel has already gone up to E3 stepping? They may iterate upon the tiles further, so any data we get on Sapphire Rapids now is probably not 100% accurate to what will eventually be the commercial product. Assuming it ever gets launched.

 

[Exist50]

Allegedly Intel has already gone up to E3 stepping? They may iterate upon the tiles further, so any data we get on Sapphire Rapids now is probably not 100% accurate to what will eventually be the commercial product. Assuming it ever gets launched.

The entire purpose of a QS is to be representative of the final product, which usually follows shortly after. It wouldn't reach the QS milestone otherwise. With a proper testing environment, QS chips should give us an honest representation. Besides, at this point it's probably mostly non-core bug fixes.

 

[DrMrLordX]

The entire purpose of a QS is to be representative of the final product, which usually follows shortly after. It wouldn't reach the QS milestone otherwise. With a proper testing environment, QS chips should give us an honest representation. Besides, at this point it's probably mostly non-core bug fixes.

A QS from before a product delay is not going to be representative of the final product. Assuming the rumours are true and that Sapphire Rapids is now a 2023 product, it's safe to assume that a QS now in the hands of a leaker is not an accurate sample of what will be a commercial product.

 

[Exist50]

Assuming the rumours are true and that Sapphire Rapids is now a 2023 product

The existence of QS chips pretty much debunks that rumor. Reaching the QS milestone and being a year from completion are mutually exclusive.

 

[IntelUser2000]

And that aside, I'm pretty sure N6 is also significantly better from a technical standpoint, looking at low-mid voltage performance and especially leakage vs Intel 7. Might even be cheaper, but the economics of that are hard to know for obvious reasons. Seriously, N6 is the hammer for every nail.

Intel 7 is similar to Intel 4 in that fact that it sacrificed leakage and density characteristics to get higher performance. It might also have limited libraries. Traditionally they had a low power version but everything messed up because of process delays few years ago.

In that case N6 is better for SoC in all sorts of ways. Intel's version which was called 22FFL which is now called Intel 16 is the latest foundry process they got and the one after that is Intel 3.

Maybe Intel was reluctant to do a monolithic design on TSMC N3, and it is certainly true that if they can't find a volume product to manufacture on Intel 4, they will have to abandon being a leading edge foundry.

No, the implications are far greater. If they don't have a mass produced chip on a node, that's essentially giving up being an IDM. If Intel 4 doesn't happen, then Intel 3, 20A, 18A won't happen. No skipping is possible because these technologies are leading-edge designs and advancements are always progressive. Those that call Intel to skip nodes is unconsciously saying Intel to get out of manufacturing altogether.

Well it turns out that the chipset team loved it. They were super impressed with the ease of use and quality + availability of IP.

Wonder if this has anything to do with hubris of the manufacturing team, being on leadership position for over a decade. Now they will have to compete on merit as their own product team might want to use external manufacturing.

Semianalysis article about that was pretty revealing that they were treating vendors pretty badly and the manufacturing side was acting like nobody could live without them.

I don't think Apple would have ever used Intel foundry even if 10nm went as exactly as they planned. It wasn't that their process characteristics was bad that they had no foundry customers, it was that their process and the way it worked wasn't conducive to external manufacturing at all. If you want to be successful in any area, you make sure to appease the particular customer base. Up until the IDM 2.0 announcement, their fab efforts still only revolved around their needs.

It would have eventually reached a point where they had to have management turnover anyways because the problem was deeper within the company.

@jpiniero and @DrMrLordX has changed their stance to what some in the investor community would call "perma-bears".

 

[jpiniero]

The existence of QS chips pretty much debunks that rumor. Reaching the QS milestone and being a year from completion are mutually exclusive.

Unless it was delayed at the QS stage because they are unhappy with yields...

 

[DrMrLordX]

Unless it was delayed at the QS stage because they are unhappy with yields...

Or because the QS still had too many bugs. Either or.

 

[repoman27]

Just for context, around 2019, the assumption for pretty much everyone was that N3 would be ready for volume production around mid-2022, and would show up in the A16. But Intel wasn't the only one who slipped timelines, and also, N3's kinda been a mess even ignoring the delay. uzzi38 has commented on that before as well, but talk to literally anyone who's so much as evaluated it. Been a right pain.

I'll argue this point, because that was only the assumption for pretty much everyone on the internet who doesn't understand silicon production timelines. Volume production was always slated for the second half of 2022, in other words, too late for Apple to use it for that year's iPhones.

2019-10-28

Expectations are that the fab will be up and running, mass producing 3nm parts by late 2022 or early in 2023.

TSMC begins construction of next-gen 3nm fab

It is aiming for volume production from the 30 hectare facility late 2022 - to early 2023.

hexus.net

2020-4-17

This earnings call marks the first time TSMC started disclosing actual information about its 3-nanometer (N3) node. C.C. Wei says the company’s N3 remains on track with risk production scheduled for 2021. TSMC is targeting volume production in the second half of 2022.

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

fuse.wikichip.org

Apple certainly knew N3 was never going to arrive in time for the A16, which was was probably taped out in Q2'21. We also know Intel taped out the compute tile for MTL around that time, but their validation cycles tend to be longer. It seemed pretty obvious to me that Intel was targeting a Q1'23 mobile-first launch for MTL to provide a 12-month cadence following ADL. Because ADL-S launched ahead of mobile in Q4'21, it would be followed instead by RPL. RPL mobile would also launch in H1'23 to provide a hedge against the risks they were taking with MTL and a conventional monolithic SoC that could serve lower price points, SIPP, etc. This would be similar to the ICL / CML split.

Also, TSMC N3 might have looked like a "right pain" to most customers evaluating it, but for Intel design groups switching from any internally developed process from the past decade, it probably looked more like a glass of ice water in hell.

However, my original point was more that I could understand Intel's lack of appetite for the cost / risk associated with being first out the gate on an external process with decently sized monolithic SoCs that represent a significant portion of their overall revenue.

 

[repoman27]

In that case N6 is better for SoC in all sorts of ways. Intel's version which was called 22FFL which is now called Intel 16 is the latest foundry process they got and the one after that is Intel 3.

Last I checked, Intel 22FFL was an updated version of 22nm with different design rules that could offer a 16% increase in logic density over standard 22nm along with either significantly lower leakage, or drive currents approaching 14++. It's a fully DUV process that was used for the Lakefield base die.

https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/22-ffl-en-fact-sheet.pdf

TSMC N6 uses the same design rules as N7, EUV for up to 5 layers, and provides an 18% logic density increase over the original N7. Not really seeing the connection here.

edit: I realized after posting this that 22FFL or "Intel 16" is the improved n-2 node to 10nm or "Intel 7", but that still makes it n-3 to Intel 3/4.

No, the implications are far greater. If they don't have a mass produced chip on a node, that's essentially giving up being an IDM. If Intel 4 doesn't happen, then Intel 3, 20A, 18A won't happen. No skipping is possible because these technologies are leading-edge designs and advancements are always progressive. Those that call Intel to skip nodes is unconsciously saying Intel to get out of manufacturing altogether.

I may not have phrased it quite right, but the implication I was going for was exactly this—giving up on being a true IDM.

 

[jpiniero]

No, the implications are far greater. If they don't have a mass produced chip on a node, that's essentially giving up being an IDM. If Intel 4 doesn't happen, then Intel 3, 20A, 18A won't happen. No skipping is possible because these technologies are leading-edge designs and advancements are always progressive. Those that call Intel to skip nodes is unconsciously saying Intel to get out of manufacturing altogether.

Presumably Meteor Lake's CPU tile is the only volume Intel 4 product left. But even if they somehow shifted the CPU tile to TSMC, that wouldn't stop them from continuing trying to make it work internally.

 

[coercitiv]

Presumably Meteor Lake's CPU tile is the only volume Intel 4 product left. But even if they somehow shifted the CPU tile to TSMC, that wouldn't stop them from continuing trying to make it work internally.

My interpretation of what @IntelUser2000 said is that in the absence of high volumes for one advanced node, the R&D team will lack valuable findings and "field data" to confidently move on to the next node. So the lower the volume, the lower the chance to make it work.

I think it's safe to say that not having a mass produced chip on Intel 4 would inevitably send delay ripples through Intel's entire manufacturing timeline.

 

[nicalandia]

Where did you see Meteor Lake as a ‘22 product?
The first announcement from Intel has it as a ‘23 product.

He might have confused "Manufacturing Ready" H2 2022



But it has become apparent that it will not be Ready for Manufacturing until 2023


Edit.

Also a good article on Alder Lake’s Caching and Power Efficiency,

Alder Lake’s Caching and Power Efficiency

Processor caches are known to improve performance, but they also significantly influence power efficiency.

chipsandcheese.com

Interesting how Gracemont Core's L2 is on the opposite side of the L3(I noticed that long ago but never made a comment on it)

 

[Exist50]

Unless it was delayed at the QS stage because they are unhappy with yields...

There's no evidence for that. Again, they've been shipping Ice Lake server for a while, and we have Alder Lake clearly reasonably healthy.

Or because the QS still had too many bugs. Either or.

If there were bugs discovered last minute, then add another quarter or two for a new stepping, if sufficiently dire. Not a full year.

 

[Exist50]

I'll argue this point, because that was only the assumption for pretty much everyone on the internet who doesn't understand silicon production timelines. Volume production was always slated for the second half of 2022, in other words, too late for Apple to use it for that year's iPhones.

The first article you quote was about the completion of a new factory, while the second is from well into 2020. And Q3 volume production might still be enough to squeak out a Mac chip for late in the year. TSMC has been very consistent about their public communications, which is commendable, but that doesn't mean their partners don't have their own expectations.