Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

The claim is that Meteor Lake got delayed from end of '22 to somewhere in mid-2023.

It says they are talking about delaying mass production until the end of 23. The actual launch would have to be 3-4 months after that at least. The earlier expectation was that they would start mass production at the end of the year for a middle of 23 paper launch of the M.

That they would also move the CPU chiplet to TSMC is indeed sketchy if they haven't already started.

Edit: That would also include their TSMC orders, ie: the N5 and N3 chiplets were scheduled for the end of this year and presumably TSMC can still fulfill that. But with no CPU chiplet there's nothing to sell.

 

[Exist50]

the thing is..

The max it's 14 cores. 6P + 8E Cores, so are those Off Die LP E Cores going to count towards the Total CPU on the marketing slides? Or are they more like Co-Processors? I mean that HUGE SOC tile does have space for additional 4 LP E cores but that would mean that the Meteor Lake would be 6P + 8E + 4 LP E?

Seems like they're simply not advertising them for that 6+8 number, since it's really 6+8+2, but how Intel marketing decides to spin things by the time they're actually released? Who knows.

The 6P+8E are treated as a single monolithic die connected thru L3 Ring Bus, but the Off die LP E cores could be treated as a separate NUMA node. But it will depend on Intel glue them together, Intel could use the word "logically monolithic"

I doubt they merit being treated like a separate NUMA node, but it'll be interesting to see how coherency is managed. Will they even let them be used at the same time as the compute die? Not sure.

 

[Exist50]

It says they are talking about delaying mass production until the end of 23. The actual launch would have to be 3-4 months after that at least. The earlier expectation was that they would start mass production at the end of the year for a middle of 23 paper launch of the M.

That they would also move the CPU chiplet to TSMC is indeed sketchy if they haven't already started.

Edit: That would also include their TSMC orders, ie: the N5 and N3 chiplets were scheduled for the end of this year and presumably TSMC can still fulfill that. But with no CPU chiplet there's nothing to sell.

The wording seems rather ambiguous, since they mention both volume production and launch before talking about the delay to end of '23. But either way, I think moving Redwood Cove + Crestmont to N3 is basically impossible in this timeframe. Lion Cove + Skymont, however, were already planned to be on N3 towards the end of '23 for Arrow Lake. Perhaps using N3 for the entirety of the Arrow Lake volume would fit?

 

[pakotlar]

https://twitter.com/x/status/1545218052207177729

Surprise, Surprise. Intel 4 is a trainwreck and they are forced to abandon the Meteor Lake paper launch. They might also be forced to fab the TSMC chiplets with no product to put it in because they were dumb enough to not dual source the CPU chiplet.

The amount of catastrophizing in this thread is hilarious. They are on track or ahead compared to all timelines released in the past 2 years.

 

[jpiniero]

The wording seems rather ambiguous, since they mention both volume production and launch before talking about the delay to end of '23. But either way, I think moving Redwood Cove + Crestmont to N3 is basically impossible in this timeframe. Lion Cove + Skymont, however, were already planned to be on N3 towards the end of '23 for Arrow Lake. Perhaps using N3 for the entirety of the Arrow Lake volume would fit?

I wouldn't be surprised if the Meteor Lake chiplets aren't theoretically compatible with any future products.

The amount of catastrophizing in this thread is hilarious. They are on track or ahead compared to all timelines released in the past 2 years.

In case you've been under a rock, Intel loves to talk up stuff to shareholders... then reality sets in.

 

[JasonLD]

The wording seems rather ambiguous, since they mention both volume production and launch before talking about the delay to end of '23. But either way, I think moving Redwood Cove + Crestmont to N3 is basically impossible in this timeframe. Lion Cove + Skymont, however, were already planned to be on N3 towards the end of '23 for Arrow Lake. Perhaps using N3 for the entirety of the Arrow Lake volume would fit?

End of 2023 means launch looking at the sentence, not the mass production, but still delaying the mass production by 6 months.

In case you've been under a rock, Intel loves to talk up stuff to shareholders... then reality sets in.

That is true, but you are also talking about Digitimes article.

 

[jpiniero]

but you are also talking about Digitimes article.

That's fair. But we are talking about a very very low bar. ~40 mm2 for the 2+8, and a tile design that should be very salvageable, is something that should not be a problem. Even for a process at pre-risk production.

 

[JasonLD]

That's fair. But we are talking about a very very low bar. ~40 mm2 for the 2+8, and a tile design that should be very salvageable, is something that should not be a problem. Even for a process at pre-risk production.

I believe it is due to the market conditions where crypto market crashed and PC sales about to decline by 10% this year and even further due to inflation, etc. It is probably part of series of rumors about Apple, AMD, and Nvidia trying to cut/delay orders from TSMC due to the same reason. H1 2023 for Meteor Lake didn't really make sense for its product timing anyways.

 

[IntelUser2000]

These SoC Atom cores are a good idea, but the implementation is tempered by the process choice, lack of DLVR, etc.

The leak does mention DLVR for Meteorlake. I don't know why you thought otherwise?

I honestly had expected the E cores to be used exactly for that. I find it a bit unfathomable that Intel really needs LP E cores on top of that to be able to achieve this.

The Gracemont E cores are there for efficient MT performance increase. Plus they clock at 4GHz, so the dynamic range would be way too high. They certainly did not need 8 cores if all they wanted was to use is for power management. Remember they introduced a 486-class core in Nehalem *just* for power management! So the main CPU core needed another much smaller one.

Another thing is their problem is related to the PCH powering down which has nothing to do with E cores. The LP cores are going into the SoC island which is essentially a bigger PCH.

 

[jpiniero]

H1 2023 for Meteor Lake didn't really make sense for its product timing anyways.

It does (did?). Intel marketing is obsessed with Apple.

 

[Exist50]

I wouldn't be surprised if the Meteor Lake chiplets aren't theoretically compatible with any future products.

I could theoretically see them reusing some subset for a different market, but beyond the SoC and IO tiles for Arrow Lake, doubt we'll see much flexibility.

End of 2023 means launch looking at the sentence, not the mass production, but still delaying the mass production by 6 months.

Sure, but a delay of mass production to Q2 would be in line with (at least my) expectations, which I've been repeating here some time. Delaying to Q3/Q4 would be more notable.

The leak does mention DLVR for Meteorlake. I don't know why you thought otherwise?

DLVR for the compute tile, not the SoC tile. Quite likely the LP E-cores are on VCCSA.

It does (did?). Intel marketing is obsessed with Apple.

Q2 is basically the best time for mass production. It gives enough time for bulk shipment by sea in time for Black Friday and western holiday shopping. Push too far into Q3, and only a couple of devices will have time to make it to market, and/or you need to use (expensive) air shipping.

 

[DrMrLordX]

#4 is not really possible on such a short notice, unless Intel actually ported and prepared a design already which I find hard to imagine with Intel being Intel.

There was a rumour awhile back that some engineers at Intel proposed putting Meteor Lake entirely on N3 in the event that Intel 7nm/Intel 4 proved to be inadequate. The plan was allegedly scrapped as a matter of pride. That doesn't mean that any serious work was undertaken at that time to port Meteor Lake over to N3 . . . but it could mean that there is already a faction within Intel that is amenable to the move.

 

[igor_kavinski]

The plan was allegedly scrapped as a matter of pride.

That always gets them in a pool of their own piss.

 

[repoman27]

Q2 is basically the best time for mass production. It gives enough time for bulk shipment by sea in time for Black Friday and western holiday shopping. Push too far into Q3, and only a couple of devices will have time to make it to market, and/or you need to use (expensive) air shipping.

Cycle times dragging out to 100 days, silicon produced using 4 different manufacturing processes (2 of which are still nascent) at 3 different production sites, testing and sorting 4 tiles plus an interposer, combining them all into a single 3D package, testing and sorting again... I'm guessing lead times could be a little longer than usual for this product.

 

[jpiniero]

Q2 is basically the best time for mass production. It gives enough time for bulk shipment by sea in time for Black Friday and western holiday shopping. Push too far into Q3, and only a couple of devices will have time to make it to market, and/or you need to use (expensive) air shipping.

I think the intention was to have Meteor Lake "Y" be available in time for it to be part of the 13th Gen. So available in stores in like May or June.

 

[Exist50]

There was a rumour awhile back that some engineers at Intel proposed putting Meteor Lake entirely on N3 in the event that Intel 7nm/Intel 4 proved to be inadequate. The plan was allegedly scrapped as a matter of pride. That doesn't mean that any serious work was undertaken at that time to port Meteor Lake over to N3 . . . but it could mean that there is already a faction within Intel that is amenable to the move.

I think you're referring to a story that I told a while back, but it seems like some of the details got warped over time. Back in, maybe 2019-ish, the design teams were starting to hash out what exactly Meteor Lake was to be. They basically told management, "If you want us to compete with Apple, we need to be on the best process, like they are" and looking towards the original mid-2022 production timeframe, that was N3. Management, obviously, was not thrilled with the implications of outsourcing the entire client lineup, and to a cutting edge (expensive) node at that. After some back and forth, and a very questionable top-down design decree, they ended up with more or less the Meteor Lake we see today.

So the N3 proposal was less about delays for Intel 7nm/4, and more just observing that N3 would simply be the better process, even if the original 7nm plans held. Though that said, I think the current Meteor Lake definition was concocted in no small part as a hedge against fab issues. And most of Intel's design teams have, at this point, no particular love for the fab side. They want something that actually works, as specified, when specified.

Anyway, the design teams may be open to the possibility, but porting RWC in particular is probably impossible in the timeframe rumored, so I think it's easy to dismiss that particular part of the rumor. But I could see merit in the claim that they're negotiating a different product split to compensate for delays.

 

[DrMrLordX]

I think you're referring to a story that I told a while back, but it seems like some of the details got warped over time. Back in, maybe 2019-ish, the design teams were starting to hash out what exactly Meteor Lake was to be. They basically told management, "If you want us to compete with Apple, we need to be on the best process, like they are" and looking towards the original mid-2022 production timeframe, that was N3. Management, obviously, was not thrilled with the implications of outsourcing the entire client lineup, and to a cutting edge (expensive) node at that. After some back and forth, and a very questionable top-down design decree, they ended up with more or less the Meteor Lake we see today.

It's basically the same thing. The implication of porting to N3 would be that Intel's time on the cutting edge would be over. Rather than swallowing their pride, they carried on. Might not have worked out for them.

So the N3 proposal was less about delays for Intel 7nm/4, and more just observing that N3 would simply be the better process, even if the original 7nm plans held.

Fair enough; that being said, I'm sure at least some of the designers had to have been skeptical about future nodes after the unfolding disaster that was 10nm (in 2019).

Anyway, the design teams may be open to the possibility, but porting RWC in particular is probably impossible in the timeframe rumored, so I think it's easy to dismiss that particular part of the rumor. But I could see merit in the claim that they're negotiating a different product split to compensate for delays.

The only way Intel can pull it off is if someone has already started work on the project as a hedge. That was my only reason for bringing any of that up. On the off chance that Gelsinger actually revisited the old proposal.

 

[Exist50]

The only way Intel can pull it off is if someone has already started work on the project as a hedge. That was my only reason for bringing any of that up. On the off chance that Gelsinger actually revisited the old proposal.

I remember hearing that they had a small team experimentally porting either Golden Cove or Redwood Cove to TSMC (unsure which node), but I think they canceled the exercise. Seems like they're currently porting Lion Cove to Intel 3, N3, and 20A all for release within a year or so, so do they really have resources to spare?

 

[pakotlar]

In case you've been under a rock, Intel loves to talk up stuff to shareholders... then reality sets in.

They are legally barred from doing what you're suggesting (purposefully deceiving stakeholders). They can break the law, but it would be naive to assume that is what they're doing, especially since all actual evidence points to the contrary. MLID trolling notwithstanding.

 

[moinmoin]

The Gracemont E cores are there for efficient MT performance increase.

Though they are not efficient in MT performance, only is area usage.

Plus they clock at 4GHz, so the dynamic range would be way too high.

Abused at 4GHz you mean. Above 3.2GHz the E cores are actually less efficient than the P cores. For Zen cores the dynamic range doesn't seem to be too high to cover all bases Intel still isn't able to.

Another thing is their problem is related to the PCH powering down which has nothing to do with E cores. The LP cores are going into the SoC island which is essentially a bigger PCH.

So instead finally moving the PCH into the compute block making it a true SoC they invent yet another core level? Doesn't sound like positive progress to me.

 

[jpiniero]

They are legally barred from doing what you're suggesting (purposefully deceiving stakeholders).

How many times did Intel say "10 nm is on track!!!" only to delay it?

And if you think about it, 7 nm has been delayed multiple times already. I think all the talk is partially to shareholders but also to Congress, because they want their free money. Earnings should still be good though because they will have to admit the Sapphire delay at least.

 

[pakotlar]

How many times did Intel say "10 nm is on track!!!" only to delay it?

And if you think about it, 7 nm has been delayed multiple times already. I think all the talk is partially to shareholders but also to Congress, because they want their free money. Earnings should still be good though because they will have to admit the Sapphire delay at least.

“purposefully”

 

[Markfw]

“purposefully”

Really.... They have lied so many times about so many things, that I have no idea what they did due to stupidity, and how many times it was on purpose.

Does it matter ?????

 

[Henry swagger]

Meteor lake is p-core is 15-20 better than raptor cove.. arrow lake is aiming for 45% plus greater than alder lake for p-core performance 😏

 

[IntelUser2000]

Abused at 4GHz you mean. Above 3.2GHz the E cores are actually less efficient than the P cores. For Zen cores the dynamic range doesn't seem to be too high to cover all bases Intel still isn't able to.

That is totally different from a low power island dedicated to power management. It's a completely different scale. Repeating myself, Nehalem has 486 class core just for that. Sure the LP core on Meteorlake is far more capable, but it's going to be something like Crestmont at 1GHz on a low frequency, ultra low leakage design and SoC process.

So instead finally moving the PCH into the compute block making it a true SoC they invent yet another core level? Doesn't sound like positive progress to me.

Again, an ultra low power core just for power management. The PCH already has some microcontroller for various duties such as power management. You don't see it because it's transparent.

Not doing a true SoC has Intel-specific reasons I outlined before in addition to the whole industry moving to the chiplet/tile arrangement. Also they can use a process better tailored to SoC tile. Remember they are using HP Intel 4 tiles with higher performance but higher leakage current and power.