Discussion Intel current and future Lakes & Rapids thread

[Saylick]

I thought that was N4 or 5.

Oh that's right.

Wait, what?

Making the SOC on the leading edge TSMC node? Isn't that die mostly IO and other stuff that doesn't scale well? Why would they use a leading edge process?

 

[IntelUser2000]

But the short and skinny is that compute die has the P cores and the E core clusters, and the LP E cores are on the SOC die, which is on the older node (Intel 7). The idea that's been floating around is either the VPU runs off of those cores (not sure if legit), or that the LP cores are there to run the system if the workload does not require turning on the compute die, thus saving power.

The big problem with Intel platform is that the idle power has not been realistic to reach often enough to matter and also it takes a substantial effort to even make it possible.

By using a very low power x86 core dedicated for power management and idle they can reel in such scenarios which keeps the CPU package from sleeping and at the same time allow driver/firmware development to be smooth in comparison to having a real special purpose core in there.

I'm excited for the confirmation of the cores for Meteorlake. Finally it has a chance of being a good mobile chip and a trend reversal of battery life regressions since Cometlake.

 

[aigomorla]

I seem to remember a thread in the CPU forums about people using Threadripper to do professional rendering for a movie project, for example. That's lost revenue for AMD and integrators when people can "cheap out" with high-end prosumer gear.

No all they need to do is put lots and lots of RGB, watercooling pump headers, and slap the Gamer tag in front of HEDT, and they can charge more then enterprise prices for it.

On topic of this, will i be able to run 2 GPUs and 2 nvme drives on that X670 board with 7950x? Cause that is my intention /need. I mean, without compromised performance anywhere.

each gpu will be downgraded to 8x, and not run at the full 16x each.
So asking for what your asking, 16x + 8x = 24x total pci-e lanes required.
That means yes, but thats your wall there, meaning you probably can't do anymore, like add a thunderbolt 4 card, or a 10gbe nic.
And you definitely can not throw in a bifurcation card ever which is required when you want to run 4 nvme's in R0 for some insanity.

 

[DrMrLordX]

Wait, what?

Making the SOC on the leading edge TSMC node? Isn't that die mostly IO and other stuff that doesn't scale well? Why would they use a leading edge process?

Is Intel taking any significant number of N6 wafers?

No all they need to do is put lots and lots of RGB, watercooling pump headers, and slap the Gamer tag in front of HEDT, and they can charge more then enterprise prices for it.

More than 1P EPYC? Somehow I doubt that. Threadripper Pro is already charging more per socket/PCIe lane than Threadripper.

 

[Exist50]

Are these LP E Cores just down clocked E Cores?

In addition to what's been stated about them being on the SoC die, they are full fat Crestmont (maybe Gracemont), at least on Meteor Lake and Arrow Lake. Future, who knows.

Ehh? So Intel is only making the compute die and the base die for Foveros? That's interesting. It's not like they have a shortage of Intel 7 throughput. I wonder why they want to outsource that to TSMC...

Well N6 is just flat out better for the purpose (low-mid voltage, low leakage, low cost). But beyond that, you can actually buy IP on N6.

 

[Exist50]

The big problem with Intel platform is that the idle power has not been realistic to reach often enough to matter and also it takes a substantial effort to even make it possible.

By using a very low power x86 core dedicated for power management and idle they can reel in such scenarios which keeps the CPU package from sleeping and at the same time allow driver/firmware development to be smooth in comparison to having a real special purpose core in there.

I'm excited for the confirmation of the cores for Meteorlake. Finally it has a chance of being a good mobile chip and a trend reversal of battery life regressions since Cometlake.

I certainly don't expect Meteor Lake to be worse than Alder Lake. But I do think you should temper your expectations somewhat. These SoC Atom cores are a good idea, but the implementation is tempered by the process choice, lack of DLVR, etc. And more importantly, some of the much bigger overheads MTL introduces that it'll need to overcome. I think there will be much more opportunity in the Lunar Lake, or perhaps Nova Lake, timeframe.

 

[Henry swagger]

https://twitter.com/x/status/1545161161557118980

 

[uzzi38]

https://twitter.com/x/status/1545161161557118980

LMFAO

https://twitter.com/x/status/1544846281671155712

 

[itsmydamnation]

why does everyone forget poor cannon lake .......

 

[moinmoin]

They included a Quark "line" but not a Phi line.

The big problem with Intel platform is that the idle power has not been realistic to reach often enough to matter and also it takes a substantial effort to even make it possible.

By using a very low power x86 core dedicated for power management and idle they can reel in such scenarios which keeps the CPU package from sleeping and at the same time allow driver/firmware development to be smooth in comparison to having a real special purpose core in there.

I'm excited for the confirmation of the cores for Meteorlake. Finally it has a chance of being a good mobile chip and a trend reversal of battery life regressions since Cometlake.

I honestly had expected the E cores to be used exactly for that. I find it a bit unfathomable that Intel really needs LP E cores on top of that to be able to achieve this.

 

[tomatosummit]

why does everyone forget poor cannon lake .......

Palm Cove innit?
It's on the messy illustration.

 

[jpiniero]

https://twitter.com/x/status/1545218052207177729

Surprise, Surprise. Intel 4 is a trainwreck and they are forced to abandon the Meteor Lake paper launch. They might also be forced to fab the TSMC chiplets with no product to put it in because they were dumb enough to not dual source the CPU chiplet.

 

[DrMrLordX]

So Intel laid out likely over $10 billion for N3, and now they have to pay more to delay taking the wafers for two quarters? Ouch. That's gonna hurt the old pocketbook. Unless they produce all of Meteor Lake on N3 . . .

 

[igor_kavinski]

https://twitter.com/x/status/1545218052207177729

I believe point #4 to be more likely because Intel is desperate and has to do whatever it can to meet targets and control losses.

 

[nicalandia]

We all Knew Intel4 was a Flop since Granite Rapids was moved to Intel 3

 

[JasonLD]

https://twitter.com/x/status/1545218052207177729

Surprise, Surprise. Intel 4 is a trainwreck and they are forced to abandon the Meteor Lake paper launch. They might also be forced to fab the TSMC chiplets with no product to put it in because they were dumb enough to not dual source the CPU chiplet.

And 2 days ago they said Intel 4 is on its production later this year. I think #4 on that rumor alone is ridiculous enough to dismiss that entire rumor as unlikely.

 

[moinmoin]

As I noted in the Raptor Lake thread:

Intel going mixed node chiplets then delaying is certainly bound to become a juicy mess. Though knowing Intel I'd expect Intel to stockpile "early" dies and pretend everything worked as planned once all chiplets are up to speed and can be launched as complete chips.

I believe point #4 to be more likely because Intel is desperate and has to do whatever it can to meet targets and control losses.

#4 is not really possible on such a short notice, unless Intel actually ported and prepared a design already which I find hard to imagine with Intel being Intel.

 

[Exist50]

LMFAO

https://twitter.com/x/status/1544846281671155712

LMAO indeed. Why do people waste they time coming up with diagrams for such nonsense?

 

[Exist50]

https://twitter.com/x/status/1545218052207177729

Surprise, Surprise. Intel 4 is a trainwreck and they are forced to abandon the Meteor Lake paper launch. They might also be forced to fab the TSMC chiplets with no product to put it in because they were dumb enough to not dual source the CPU chiplet.

I think you're reading this all wrong. The claim is that Meteor Lake got delayed from end of '22 to somewhere in mid-2023. That's easily believable. I've been skeptical of mass production any time before Q2 to begin with. But that's irrespective of Intel 4.

The supposed problem is that Intel had orders for N3 in that timeline, and those now have to be pushed backed back and face penalties. The solution being proposed is basically for Intel to placate TSMC by ordering additional N3 volume to compensate. I think this is very unlikely with the timeline and products detailed in the article.

 

[igor_kavinski]

Or Intel could flood the market with cheap chips, breaking even or making a tiny profit. Better than making loss.

 

[nicalandia]

It says "LP E-cores" and references "Low-power island CPU offload". I.e. these are the SOC die Atom cores (Gracemont or Crestmont) I've mentioned previously. @dullard, I recall you were skeptical of their existence. Hopefully this puts those doubts to rest.

the thing is..

The max it's 14 cores. 6P + 8E Cores, so are those Off Die LP E Cores going to count towards the Total CPU on the marketing slides? Or are they more like Co-Processors? I mean that HUGE SOC tile does have space for additional 4 LP E cores but that would mean that the Meteor Lake would be 6P + 8E + 4 LP E?

 

[igor_kavinski]

Are the LP e-cores worth discussing from a performance standpoint? Are they even going to add something of value to multicore benchmark scores? I would prefer that they be reserved exclusively by the critical OS threads so they don't take time slices away from the user threads.

 

[nicalandia]

Are the LP e-cores worth discussing from a performance standpoint?

That will depend how the new Thread Director uses them. even if they are low clocked Gracemonts they should add MT performance

 

[igor_kavinski]

The inter-thread communication between three separate core clusters has got to be a challenge, I imagine, due to the latency involved.

 

[nicalandia]

The inter-thread communication between three separate core clusters has got to be a challenge, I imagine, due to the latency involved.

The 6P+8E are treated as a single monolithic die connected thru L3 Ring Bus, but the Off die LP E cores could be treated as a separate NUMA node. But it will depend on Intel glue them together, Intel could use the word "logically monolithic"