I thought that was N4 or 5.
Wait, what?Oh that's right.
But the short and skinny is that compute die has the P cores and the E core clusters, and the LP E cores are on the SOC die, which is on the older node (Intel 7). The idea that's been floating around is either the VPU runs off of those cores (not sure if legit), or that the LP cores are there to run the system if the workload does not require turning on the compute die, thus saving power.
I seem to remember a thread in the CPU forums about people using Threadripper to do professional rendering for a movie project, for example. That's lost revenue for AMD and integrators when people can "cheap out" with high-end prosumer gear.
On topic of this, will i be able to run 2 GPUs and 2 nvme drives on that X670 board with 7950x? Cause that is my intention /need. I mean, without compromised performance anywhere.
Wait, what?
Making the SOC on the leading edge TSMC node? Isn't that die mostly IO and other stuff that doesn't scale well? Why would they use a leading edge process?
No all they need to do is put lots and lots of RGB, watercooling pump headers, and slap the Gamer tag in front of HEDT, and they can charge more then enterprise prices for it.
In addition to what's been stated about them being on the SoC die, they are full fat Crestmont (maybe Gracemont), at least on Meteor Lake and Arrow Lake. Future, who knows.Are these LP E Cores just down clocked E Cores?
Well N6 is just flat out better for the purpose (low-mid voltage, low leakage, low cost). But beyond that, you can actually buy IP on N6.Ehh? So Intel is only making the compute die and the base die for Foveros? That's interesting. It's not like they have a shortage of Intel 7 throughput. I wonder why they want to outsource that to TSMC...
I certainly don't expect Meteor Lake to be worse than Alder Lake. But I do think you should temper your expectations somewhat. These SoC Atom cores are a good idea, but the implementation is tempered by the process choice, lack of DLVR, etc. And more importantly, some of the much bigger overheads MTL introduces that it'll need to overcome. I think there will be much more opportunity in the Lunar Lake, or perhaps Nova Lake, timeframe.The big problem with Intel platform is that the idle power has not been realistic to reach often enough to matter and also it takes a substantial effort to even make it possible.
By using a very low power x86 core dedicated for power management and idle they can reel in such scenarios which keeps the CPU package from sleeping and at the same time allow driver/firmware development to be smooth in comparison to having a real special purpose core in there.
I'm excited for the confirmation of the cores for Meteorlake. Finally it has a chance of being a good mobile chip and a trend reversal of battery life regressions since Cometlake.
I honestly had expected the E cores to be used exactly for that. I find it a bit unfathomable that Intel really needs LP E cores on top of that to be able to achieve this.The big problem with Intel platform is that the idle power has not been realistic to reach often enough to matter and also it takes a substantial effort to even make it possible.
By using a very low power x86 core dedicated for power management and idle they can reel in such scenarios which keeps the CPU package from sleeping and at the same time allow driver/firmware development to be smooth in comparison to having a real special purpose core in there.
I'm excited for the confirmation of the cores for Meteorlake. Finally it has a chance of being a good mobile chip and a trend reversal of battery life regressions since Cometlake.
Palm Cove innit?why does everyone forget poor cannon lake .......
I believe point #4 to be more likely because Intel is desperate and has to do whatever it can to meet targets and control losses.
Surprise, Surprise. Intel 4 is a trainwreck and they are forced to abandon the Meteor Lake paper launch. They might also be forced to fab the TSMC chiplets with no product to put it in because they were dumb enough to not dual source the CPU chiplet.
Intel going mixed node chiplets then delaying is certainly bound to become a juicy mess. Though knowing Intel I'd expect Intel to stockpile "early" dies and pretend everything worked as planned once all chiplets are up to speed and can be launched as complete chips.
#4 is not really possible on such a short notice, unless Intel actually ported and prepared a design already which I find hard to imagine with Intel being Intel.I believe point #4 to be more likely because Intel is desperate and has to do whatever it can to meet targets and control losses.
LMAO indeed. Why do people waste they time coming up with diagrams for such nonsense?
I think you're reading this all wrong. The claim is that Meteor Lake got delayed from end of '22 to somewhere in mid-2023. That's easily believable. I've been skeptical of mass production any time before Q2 to begin with. But that's irrespective of Intel 4.
Surprise, Surprise. Intel 4 is a trainwreck and they are forced to abandon the Meteor Lake paper launch. They might also be forced to fab the TSMC chiplets with no product to put it in because they were dumb enough to not dual source the CPU chiplet.
It says "LP E-cores" and references "Low-power island CPU offload". I.e. these are the SOC die Atom cores (Gracemont or Crestmont) I've mentioned previously. @dullard, I recall you were skeptical of their existence. Hopefully this puts those doubts to rest.
That will depend how the new Thread Director uses them. even if they are low clocked Gracemonts they should add MT performanceAre the LP e-cores worth discussing from a performance standpoint?