Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

Intel Looking to Mirror M1's Manufacturing Process for 'Meteor Lake' CPUs - MacRumors

Old rumor and you all probably know about it but this would allow Intel to fight fire with fire. I hope it happens.

Dual sourcing the CPU chiplet at TSMC makes too much sense for Intel to do that.

 

[JasonLD]

Intel Looking to Mirror M1's Manufacturing Process for 'Meteor Lake' CPUs - MacRumors

Old rumor and you all probably know about it but this would allow Intel to fight fire with fire. I hope it happens.

Digitimes throws way too many stuff at the wall to see what sticks. Nvidia was using TSMC for Ampere according to them also.

 

[jpiniero]

Nvidia was using TSMC for Ampere according to them also.

Well, they did release Ampere products using TSMC...

 

[JasonLD]

Well, they did release Ampere products using TSMC...

*gaming
Shame on me forgetting the generation where Nvidia uses same architecture name for Pro/Gaming. Digitimes did say Nvidia is going to use TSMC for gaming GPUs also.

Oh, Digitimes also said Nvidia will shift RTX30 series GPUs from Samsung 8nm to TSMC 7nm last year as well. (wouldn't be a bad thing to happen, but that never happened)

 

[Doug S]

While a 1+1 fin library seems incredible (coming from a 2+3 library), I wouldn't yet rule it out given the 2.4x density claim by BK in 2018. In addition, going from a 4+5 (9 fin) to 3+3 (6 fin) library from Intel 7 to Intel 4 already shows that Intel can do both fin depopulation as well achieve its performance targets simultaneously.

You're using a density claim from 2018 to guess what Intel may do in 2023? You don't think maybe all the 10nm problems might have caused them to be a bit less aggressive? Especially considering the short timeline between Intel 4 / Intel 3 / 20A / 18A they are projecting?

The fact they previously did a fin depopulation may make another one less likely, given that it gets harder the fewer fins you have. I certainly see no possible scenario where they could jump to 1+1.

 

[uzzi38]

Digitimes throws way too many stuff at the wall to see what sticks. Nvidia was using TSMC for Ampere according to them also.

Correction: Digitimes will throw as much at the wall as possible provided the end result is TSMC makes more money in some way or another.

 

[Henry swagger]

https://twitter.com/x/status/1536700762432098305

Cool chip

 

[moinmoin]

"the silicon is just 1,92 mm²"
Perfect use case for Intel 4! /scnr

 

[DrMrLordX]

Intel Looking to Mirror M1's Manufacturing Process for 'Meteor Lake' CPUs - MacRumors

Old rumor and you all probably know about it but this would allow Intel to fight fire with fire. I hope it happens.

I've been expecting Intel to struggle with Intel 4 and Intel 3 volume. No surprises there.

Seriously??? I wont comment on that poster, other than to say he is the last person I would look to for anything unbiased about Intel.

Yes. He knows a lot about Intel's insistence on "old school" design techniques versus synthetics. Routing via synthetic AI-driven planning versus routing by hand may be exactly the reason for the observed phenomena. And may also be one reason why Golden Cove is so area-inefficient. But he hasn't logged on since January, and I doubt he'll chime in on it.

 

[Ajay]

I've been expecting Intel to struggle with Intel 4 and Intel 3 volume. No surprises there.

In their favor, at least they went to N4 before N3 - and didn't swing for the fences this time. That should improve their odds of having a competitive N3 process on which to build a more competitive CPU stack (and give them more time to get extra EUV lithography equipment installed). Despite their recent track record, I really hope Intel doesn't completely blow it.

 

[JasonLD]

I've been expecting Intel to struggle with Intel 4 and Intel 3 volume. No surprises there.

Intel EUV machine count should be around 20 by 2023 and that should be enough for at least 45k Wpm. Considering Intel’s plan is to use their own process for compute only, I don’t think there is going to be a problem supplying their own product at least

 

[TESKATLIPOKA]

Core i7-1255U review.
Not as bad as I expected.

uzzi38: I meant performance. Battery life in this review was underwhelming.

 

[DrMrLordX]

Intel EUV machine count should be around 20 by 2023 and that should be enough for at least 45k Wpm. Considering Intel’s plan is to use their own process for compute only, I don’t think there is going to be a problem supplying their own product at least

Hmm really? That contradicts earlier reports. Where is Intel getting all the extra equipment?

In their favor, at least they went to N4 before N3 - and didn't swing for the fences this time. That should improve their odds of having a competitive N3 process on which to build a more competitive CPU stack (and give them more time to get extra EUV lithography equipment installed). Despite their recent track record, I really hope Intel doesn't completely blow it.

Well yeah. TBH I don't see anything wrong with them using N4 to bolster supply. And it gels with the idea of them using N3 later on for Arrow Lake. But it's funny how hush-hush Intel is about how and where they're using TSMC nodes in public presentations. They want to talk up their own manufacturing.

 

[uzzi38]

Core i7-1255U review.
Not as bad as I expected.

I'm not sure I agree. Those battery life figures are far lower than I was expecting. Renoir in essentially the same chassis (but 16:9 display instead of 16:10) has a very significant lead over ADL-U there. That's well below what I was hoping to see, I was hoping ADL-U would be around the level of Tiger Lake and Renoir/Cezanne.

 

[uzzi38]

Neve mind, I wasn't aware of this until a few minutes ago but apparently all of the 12x5U chips are still using the 6+8 die. The 2+8 die is apparently entirely MIA. In which case, the poor battery life is not very surprising after all.

 

[jpiniero]

Neve mind, I wasn't aware of this until a few minutes ago but apparently all of the 12x5U chips are still using the 6+8 die. The 2+8 die is apparently entirely MIA. In which case, the poor battery life is not very surprising after all.

You sure? It would make sense from a yield harvest POV. Kind of assumed they were using both.

There are 9W U laptops coming out soon... those have to be using the 2+8 die. Those would presumably be pretty uncommon though.

 

[uzzi38]

You sure? It would make sense from a yield harvest POV. Kind of assumed they were using both.

There are 9W U laptops coming out soon... those have to be using the 2+8 die. Those would presumably be pretty uncommon though.

Yeah, Andrei's the one that pointed it out and looking at Ark it makes sense. The 12x5U parts all have higher TDPs, they support both DDR and LPDDR and they all support more PCIe lanes.

Here's an example of one 1255U laptop under the heatsink. It's very clearly not the -M silicon.

When we see laptops using 2+8 silicon, we'll know.

 

[JasonLD]

Hmm really? That contradicts earlier reports. Where is Intel getting all the extra equipment?

Intel can get around with 12 EUV systems for 45k wpm. Intel needs around 12 layers for its Intel 4 process. 1 EUV layer requires 1 EUV system for 45k wpm.
I don't think EUV capacity will be the bottleneck for Intel 4.

 

[dangerman1337]

RE: Intel 4/3 transistor density discussion
*snip*

If Intel 3 is 240 Mtr then I wonder how much will 20 & 18A will be over that? Because if Intel was to gain customers away from TSMC who has Apple basically hogging vast majority of any new node for 1 or even 2 years with TSMC 5nm derived nodes they'll have to get density parity. If 18 or even 20A is on par with TSMC 2nm they'll make bank.

 

[Ajay]

If Intel 3 is 240 Mtr then I wonder how much will 20 & 18A will be over that? Because if Intel was to gain customers away from TSMC who has Apple basically hogging vast majority of any new node for 1 or even 2 years with TSMC 5nm derived nodes they'll have to get density parity. If 18 or even 20A is on par with TSMC 2nm they'll make bank.

Intel isn't going to make 'bank' on anything IDM related till:

1) It proves with smaller customers that they can in fact integrate with customer tools, deliver on cost, performance and yield targets.
2) Accomplishing 1, get at least one large customer's leading edge design up on Intel's IDM and meet or exceed customer expectations.
3) Use that success to attract multiple leading edge (n, n-1) designs with the same success rate as above.

So, not happening tomorrow. It will 2-4 years of working with a customer till final silicon is in HVM, depending on the required parametrics, complexity and size of the final silicon.

Also, final silicon designs never meet the maximum density promoted by a company, be that is usually based only on logic scaling from a small test chip (usually ARM cores for TSMC and Samsung, maybe ATOM cores with Intel).

 

[jpiniero]

When we see laptops using 2+8 silicon, we'll know.

Dell has an XPS 13 laptop for sale with the 1230U that you can order but doesn't ship until July.

 

[IntelUser2000]

Well yeah. TBH I don't see anything wrong with them using N4 to bolster supply. And it gels with the idea of them using N3 later on for Arrow Lake. But it's funny how hush-hush Intel is about how and where they're using TSMC nodes in public presentations. They want to talk up their own manufacturing.

I am not 100% sure but based on context, @Ajay is saying Intel 4 when he says "N4" and Intel 3 when he says "N3"?

Arrowlake has Intel 20A and N3-plus whatever the plus might end up being.

As far as I can recollect, Intel was in the lead for nearly a decade. Pretty much from the introduction of Intel 45nm in 2007 until TSMC and Samsung 10nm arrived in 2017.

What I meant was that past is often looked as more positive it really was, just like how 14nm was said to be awesome and same with Skylake, when some of us didn't think Skylake was super impressive on the day of launch nevermind 5 years after release date. For me Skylake was "meh" and 14nm overall was disappointing. I didn't think 22nm was impressive either - after all they used all the performance gains for Atom anyway.

Intel's process lead lasted two decades, not one. Their aluminum interconnect process at 0.18u had better performance characteristics than AMD's 0.18u copper. They had better performance characteristics than AMD using SOI, while being cheaper because it wasn't using one. When they caught up in theoretical metrics then they had even greater lead. But Intel was already fat and culture was degraded for quite some time now. All it needed was the last bastion of Intel's strength to reach the point of hubris where they had to fall.

@Exist50 By in itself it doesn't, but I believe it definitely does when you combine with more advanced power management like the dedicated Atom block. It's an enabler for sure. We know Atom didn't take advantage of the integrated memory controller until Silvermont, despite all blocks being on-die. But the potential was there.

Without this, they have no dream of catching up to ARM in battery life, not even AMD.

 

[IntelUser2000]

What happened about Intel and mobile and most think it should have been done: Paul Otellini rejected making Smartphone chips for Apple because he severely underestimated the volume. Sure, the cost per chip was low but volume was great. Then the solution was if he accepted making chips for Apple right?

What should have happened: Apple should have never needed to ask Intel in the first place. Their Atom project would have had super low platform power necessary to fit into Smartphones and Intel would have done it organically, out of naturally expanding the computing market. Paul Otellini didn't listen because Intel was absolutely nowhere near the point of getting chips in mobile. Medfield, the first chip that showed that x86 can compete with ARM in battery life, was introduced in 2012, 4 years after the first Atom and 5 years after the iPhone.

If the battery life competitive chip was Silverthorne, even if it was a year after iPhone's introduction, Intel would have took the place of Qualcomm. The performance was way better than the iPhone first gen so Apple might have took Intel.

 

[Ajay]

I am not 100% sure but based on context, @Ajay is saying Intel 4 when he says "N4" and Intel 3 when he says "N3"?

Arrowlake has Intel 20A and N3-plus whatever the plus might end up being.

Oops! Good catch, yes I was referring to Intel nodes. We need a new abbreviation system IN4 for Intel, SN4 for Samsung and TN4 for TSMC?? IDK…

 

[IntelUser2000]

Oops! Good catch, yes I was referring to Intel nodes. We need a new abbreviation system IN4 for Intel, SN4 for Samsung and TN4 for TSMC?? IDK…

Remember i486 on 486 CPUs?

i4, t4, s4?