Discussion Intel current and future Lakes & Rapids thread

[Ajay]

I think the scaling is greater for High performance library which would be more important for Intel, which is actually closer to 2x scaling. View attachment 63016

https://twitter.com/i/web/status/1536168118057320450

Holy smokes! I really thought that Intel 4 was just an evolution of Intel 7. If this diagram is correct - then I was woefully misinformed. That reduction in library height for an HP process is totally unexpected. Maybe Intel's process group's new leadership has truly got themselves 'unstuck' and are burning the midnight oil. If this scales well and yields well - I’ll be impressed and eating some crow.

Honestly, I’ll be happy if it is right. It was embarrassing and an economic blow to US for one of our tech giants to fall so far behind in technology.

Also, I’ll owe @Henry swagger an apology - if actual products are equally impressive.

 

[jpiniero]

Holy smokes! I really thought that Intel 4 was just an evolution of Intel 7. If this diagram is correct - then I was woefully misinformed.

Intel has always said that I4 is the 7 nm process renamed. Well, it might be a gutted version of it, but it's not derived from 10 nm.

Here's an article from 2018 quoting Intel as saying that 7 nm is intended to be a normal 2x shrink:

Intel: EUV-Enabled 7nm Process Tech is on Track

www.anandtech.com

 

[mikk]

The Area reduction is only 25% on the compute side(Compute Tile vs Compute section: Alder Lake vs Meteor Lake)

Meteor Lake doesn't use the same core architecture.

 

[nicalandia]

Meteor Lake doesn't use the same core architecture.

What are you on about? Meteor Lake(Redwood Cove Core) is an evolution of Alder Lake/Raptor Lake on a smaller node. They look Identical in every way possible.

 

[repoman27]

I'm pretty amazed by the number of people posting positive responses to the Intel 4 density disclosures. They're horrible—they are not even close to BK's "2.4x" figure from Q1 2018 or even the 2x from the 2019 Investor Meeting. The fact that they're not disclosing cell height for the HD library or density metrics directly comparable to what they touted during the run-up to 10nm is a blatant red flag.

metric	Intel 10nm	Intel 4 (low)	Intel 4 (high)	scaling
fin pitch (nm)	34​	30​	30​	0.88x​
contacted poly pitch (nm)	54​	50​	50​	0.93x​
HD cell height (fins)	8​	6​	6​	0.66x​
HP cell height (fins)	12​	8​	8​	0.59x​
HD density (MTr/mm²)	100.8​	164.4​	173.1​	1.63-1.72x​
HP density (MTr/mm²)	67.2​	123.3​	129.8​	1.84-1.93x​
HD SRAM Cell (µm²)	0.0312​	0.0240​	0.0240​	0.77x​
HC SRAM Cell (µm²)	0.0441​	0.0300​	0.0300​	0.68x​

I included both low and high estimates for Intel 4 depending on what the scan flip flop cell looks like. So yay, Intel 4 arriving in client products in 2023 *might* be able to match TSMC N5 from 2020 in density.

 

[JoeRambo]

So yay, Intel 4 arriving in client products in 2023 *might* be able to match TSMC N5 from 2020 in density.

The keyword here is Intel. You know the company that continued to shove us 2014's 14nm for 7 years and is still selling server CPUs on it.
So by their horrible standards getting Intel 4 in 2023 is important if uninspired advance.

The actual scaling is as always incredibly hard to quantify, as it depends on amount of login/SRAM/marketing department cunning stat etc. Even if we take TSMC N5 density as some "poster" child, AMD is releasing Zen4 sometime this year on it, and i think it is same ~70mm^2 deal per chiplet, not showing any amazing scaling for SRAM, nor logic for what is mostly the same CPU with AVX512 and 32MB of L3

 

[repoman27]

The keyword here is Intel. You know the company that continued to shove us 2014's 14nm for 7 years and is still selling server CPUs on it.
So by their horrible standards getting Intel 4 in 2023 is important if uninspired advance.

The actual scaling is as always incredibly hard to quantify, as it depends on amount of login/SRAM/marketing department cunning stat etc. Even if we take TSMC N5 density as some "poster" child, AMD is releasing Zen4 sometime this year on it, and i think it is same ~70mm^2 deal per chiplet, not showing any amazing scaling for SRAM, nor logic for what is mostly the same CPU with AVX512 and 32MB of L3

Here are comparable numbers for TSMC N5:

metric	Intel 4	TSMC N5
fin pitch (nm)	30​	30​
contacted poly pitch (nm)	50​	48​
HD cell height (fins)	6​	6​
HP cell height (fins)	8​	7.5​
HD density (MTr/mm²)	164.4​	171.3​
HP density (MTr/mm²)	123.3​	137.0​
HD SRAM Cell (µm²)	0.0240​	0.0210​
HC SRAM Cell (µm²)	0.0300​	0.0250​

There's no winning for Intel here. Not to mention that TSMC also has N4 with a 6% optical shrink and plenty of performance improvements this year. Furthermore, Intel's MTL CPU tile is not even remotely comparable to some of the stuff that has already shipped on N5, and will potentially be sharing an interposer with TSMC N3/4/5P tiles!

 

[dullard]

metric	Intel 10nm	Intel 4 (low)	Intel 4 (high)	scaling
HP density (MTr/mm²)	67.2​	123.3​	129.8​	1.84-1.93x​

I included both low and high estimates for Intel 4 depending on what the scan flip flop cell looks like.

Can you explain why even your high estimate (1.93x) is lower than the 2x that is still being claimed by Intel? https://cdn.mos.cms.futurecdn.net/MT4sgh4LAxC3ePoEeZBDyd-970-80.jpg.webp

 

[lightisgood]

10nm SF loosened their gate-pitch. However, TGL is much better than ICL.
Density is one thing. Process's value is another.

Intel 7 is good. Intel 4 must be great.

 

[Henry swagger]

Here are comparable numbers for TSMC N5:

metric	Intel 4	TSMC N5
fin pitch (nm)	30​	30​
contacted poly pitch (nm)	50​	48​
HD cell height (fins)	6​	6​
HP cell height (fins)	8​	7.5​
HD density (MTr/mm²)	164.4​	171.3​
HP density (MTr/mm²)	123.3​	137.0​
HD SRAM Cell (µm²)	0.0240​	0.0210​
HC SRAM Cell (µm²)	0.0300​	0.0250​

There's no winning for Intel here. Not to mention that TSMC also has N4 with a 6% optical shrink and plenty of performance improvements this year. Furthermore, Intel's MTL CPU tile is not even remotely comparable to some of the stuff that has already shipped on N5, and will potentially be sharing an interposer with TSMC N3/4/5P tiles!

Anantech has a article up.. intel 4 is high performance cells only no high density cells as those will be in intel 3 node.. intel hp cells are 180mmt not your values

 

[repoman27]

Can you explain why even your high estimate (1.93x) is lower than the 2x that is still being claimed by Intel? https://cdn.mos.cms.futurecdn.net/MT4sgh4LAxC3ePoEeZBDyd-970-80.jpg.webp

Intel was comparing cell height x CPP, not MTr/mm²—the metric they all said we should use when they were actually ahead of TSMC.

 

[JasonLD]

Intel was comparing cell height x CPP, not MTr/mm²—the metric they all said we should use when they were actually ahead of TSMC.

Using CPP x CH number, Inter 4 is right between TSMC N5 and N3, closer to N3.

Intel 4 Deep Dive - Semiwiki

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12). “Intel 4 CMOS...

semiwiki.com

 

[repoman27]

Anantech has a article up.. intel 4 is high performance cells only no high density cells as those will be in intel 3 node.. intel hp cells are 180mmt not your values

Yeah, OK, so that just makes it worse. Intel renamed 7nm with HP library "Intel 4" and 7nm with HD library "Intel 3". I guess that's one way to get to 5 nodes in 4 years. My numbers for Intel 4 HD should be right for Intel 3. Do you have a source for that 180 number?

 

[repoman27]

Using CPP x CH number, Inter 4 is right between TSMC N5 and N3, closer to N3.

Only if you completely ignore the fact that there are higher density libraries available on N5.

That article did have a bunch of good info in it though, thanks for the link. My numbers were based on four-year-old estimates by David Schor without any data from reverse engineering.

The other thing that inflates Intel's scaling claims is that they compared to Intel 7 rather than earlier 10nm nodes, which slacks the CPP from 54 to 60 nm.

 

[Exist50]

Is it even confirmed that Intel 3 will have a high density library? They've previously mentioned "Denser HP library", but nothing explicitly about HD. Like, one would assume, but...

 

[DisEnchantment]

Is it even confirmed that Intel 3 will have a high density library? They've previously mentioned "Denser HP library", but nothing explicitly about HD. Like, one would assume, but...

Intel 3 will have 2 Fin HD library and IO libs.
Intel 4 is not bad, it is big improvement over the 4 fin Intel 7 as used on ADL. But it does not have IO or HD lib, but good enough for internal consumption since apparently Intel use 4 Fin designs everywhere on Intel 7
If they keep same clocks they are going to get 40% efficiency gains. Not bad, as long as they are achieving what they said they did on the actual device.
If they get the chiplet tech working well, they could stitch tiles and not be bothered as much by yields. They can use other foundry nodes for SoC/IO tiles until Intel 3.

 

[jpiniero]

If they get the chiplet tech working well, they could stitch tiles and not be bothered as much by yields.

It could still be bothersome. They might be able to get something out of most Meteor Lake CPU tiles, but surely Intel won't be happy if we are talking about cutting most to 1+4 or 0+4.

 

[Ajay]

Intel has always said that I4 is the 7 nm process renamed. Well, it might be a gutted version of it, but it's not derived from 10 nm.

Here's an article from 2018 quoting Intel as saying that 7 nm is intended to be a normal 2x shrink:

Intel: EUV-Enabled 7nm Process Tech is on Track

www.anandtech.com

My bad. I've focused most of my attention on AMD and TSMC over the past few years and have only been tacitly following Intel's (mostly disappointing) developments. I thought the company was so broken, that it would never recover. As such, any progress look like a win to me. As in, maybe they do have a chance at reaching node parity in a few years or not, we'll see.

 

[Henry swagger]

https://twitter.com/i/web/status/1536169584767774725

Intel 3 will be available for customers like nvidia.. jensen already said they.ll use intel nodes in the future

 

[mikk]

What are you on about? Meteor Lake(Redwood Cove Core) is an evolution of Alder Lake/Raptor Lake on a smaller node. They look Identical in every way possible.

I'm saying it's not the same core and therefore you cannot simply assume Intel 4 over Intel 7 is only a 25% scaling just because Redwood Cove scaled down 25%. There are some analysis regarding Redwood Cove, you might have a look at this. They can beef up various parts of the core without any obvious differences on a die shoot like this. Another thing is that Crestmont scaled down roughly 34% which implies it's a smaller evolution over Gracemont than Redwood Cove over Golden Cove.

 

[Doug S]

Intel 3 will be available for customers like nvidia.. jensen already said they.ll use intel nodes in the future

With everyone going to chiplets, declarations that a company will use a certain foundry are even less useful than they were before. Use Intel for what? The difference between using Intel for an 800 mm^2 monolithic GPU, using Intel for one of the chiplets in a new chiplet based GPU, and using Intel for a GPU designed for embedded markets is vast.

 

[Exist50]

https://twitter.com/i/web/status/1536169584767774725

Intel 3 will be available for customers like nvidia.. jensen already said they.ll use intel nodes in the future

He said no such thing.

 

[FangBLade]

https://twitter.com/i/web/status/1536169584767774725

Intel 3 will be available for customers like nvidia.. jensen already said they.ll use intel nodes in the future

I hope Intel node won't redacted up Nvidia plans just like it did to Intel-s. Nvidia and their CEO are too succesful to Intel, and Intel isn't reliable partner, especially with node plans. Delay is Intel trademark, so Huang will be very careful. And Huang dind't say they will use Intel nodes in future, read again.





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esquared
Anandtech Forum Director

 

[AMDK11]

What are you on about? Meteor Lake(Redwood Cove Core) is an evolution of Alder Lake/Raptor Lake on a smaller node. They look Identical in every way possible.

View attachment 63035

View attachment 63033

I dare say you are wrong. First of all, both photos are of different quality and based on them it is impossible to compare the logic of the x86 core. Secondly, there are better quality pictures of the RedwoodCove and GoldenCove core structure, on the basis of which the analysis that was made shows changes in Frontend, Backend, Integer and Load / Store. I can assure you that probably the roughly 18% higher IPCs over RaptorCove did not come out of thin air. Higher IPC is an extended and rebuilt x86 core and I assure you that I am almost sure that RedwoodCove is quite a big expansion and rebuilding of the x86 core, as you will see over time.

 

[moinmoin]

I'm saying it's not the same core

Btw. this touches on something I'm curious about: die shots by Intel chips are still looking very rigid with still a lot of area spent on ring and mesh routes etc. With other chip designers changes to the look due to AI optimizes block and automated routing have made specific areas and block look way more messy and organic. It may be indeed a resolution thing, but looking at common die shots by Intel over the past decade or so one could easily get the impression there still haven't been fundamental changes to the layout (unlike e.g. the Zen core going from Zen 2 to 3 where the AI optimized blob changed shape and there appeared quite some dark silicon around it). Obviously "no changes" can't be as we know there have been quite some changes. But why the seeming rigidity? Isn't that additional effort better spent elsewhere?