Discussion Intel current and future Lakes & Rapids thread

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ashFTW

Senior member
Sep 21, 2020
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I went back and read the exchange

you just got slapped mate.....

Your position of Intel 10nm server delivery is fine , you think 80% of intels clients want to buy 5 year old 14nm Cores? .
Glad you think so! LOL. That guy said Intel can’t make 10nm anything. Icelake volume at this point is actually greater than all of AMD server volume. It’s ramping fine, from 1M in Q4‘21 to 2M in Q1’22. It’s not going to outpace Cascade lake overnight. It doesn’t work like that.

SPR doesnt look that much better for intel, ~1600mm sq for at best 50 something cores vs 630mm sq for 40.

Also being 50 something cores sux for things like Vmware licensing , so expect most SPR in enterprise to be 32 cores ( just like all my ice lake servers are). How is intel even going to service those..... 4 tiles 1600mm for 32 cores..... Jesus.
You are making invalid assumptions. Do you really believe that XCC tile is the only one Intel will make to cover the entire chip core range from 8 to 60? I have vehemently argued against this in my previous posts. Go back and read them. Or not. No skin off my back.

But there is no denying that Intel continues to delay SPR, which should be quite frustrating for their customers and investors alike. Intel should be embarrassed. Wonder how they are going to justify these on the next earnings call. I’m personally waiting to get a 2P SPR or a 1-2P Gen4 Threadripper/EPYC workstation next, whichever meets my performance/$ needs better.

I’m vendor agnostic in my technology and investment decisions. Read my signature. AMD has made me a ton of money in the past, but currently I only hold a few hundred shares. AAPL on the other hand, that’s another story!)
 
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nicalandia

Diamond Member
Jan 10, 2019
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You have AMD's own marketing materials that have SMT off: https://www.amd.com/system/files/documents/amd-epyc-7Fx2-openfoam.pdf

This shows that in all applications tested, there are gains with lower core counts but not with higher ones: https://www.nas.nasa.gov/assets/nas/pdf/papers/NAS_Technical_Report_NAS-2015-05.pdf

You are talking about 6% gains in a specific scenario with most getting no gains or even lower with recommendations to disable SMT.
Intel would never give AMD an advantage on OpenFoam by leaving their CPUs with HT On and AMD with SMT Off.

By who cares anyways. Sapphire Rapids have been delayed yet again and it will have to compete with Genoa.



Someone tells that woman that Intel 7 is Not the same as 7-nm process
 
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IntelUser2000

Elite Member
Oct 14, 2003
8,686
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Intel would never give AMD an advantage on OpenFoam by leaving their CPUs with HT On and AMD with SMT Off.

Of course not. But it could benefit SPR few % by having HT on and benefit EPYC by having HT off.

They might have cherry picked the situation that benefits them most, but they don't always disadvantage it like that. Yes, sometimes they do, like the Kabylake-G comparison where they used single channel memory, but most of the time they don't, like when people were saying they gimped AMD by using single channel on the Ryzen vs Icelake mobile comparison when they said didn't and had dual channel on Ryzen as well.

Someone tells that woman that Intel 7 is Not the same as 7-nm process

Potential similar density, and similar performance. TSMC is calling it 7nm right?
 

jpiniero

Lifer
Oct 1, 2010
14,584
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This article is from Wednesday, but I don't think it was shared here yet. Anyway Intel has a hiring freeze in the Client Group right now. Which is claimed to be only for two weeks but probably will be longer.

The relevant point is that somewhere else I saw a suggestion that PC sales are slumping to the point where Intel might warn at some point. And their Q2 forecast was for a decrease in revenue as it is. Probally not an AMD thing but a macro thing.
 

Exist50

Platinum Member
Aug 18, 2016
2,445
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This article is from Wednesday, but I don't think it was shared here yet. Anyway Intel has a hiring freeze in the Client Group right now. Which is claimed to be only for two weeks but probably will be longer.

The relevant point is that somewhere else I saw a suggestion that PC sales are slumping to the point where Intel might warn at some point. And their Q2 forecast was for a decrease in revenue as it is. Probally not an AMD thing but a macro thing.
It's worth noting that the actual silicon development falls under the Design Engineering Group.

Also, the original article: https://www.reuters.com/technology/intel-freezes-hiring-pc-chip-decision-least-two-weeks-2022-06-08/
 

DrMrLordX

Lifer
Apr 27, 2000
21,617
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Potential similar density, and similar performance. TSMC is calling it 7nm right?

1). TSMC hasn't used "nm" in their node names since 16nm/12nm
2). Intel had a 7hm process and renamed it to Intel 4

Anyone referring to Intel 7 as a "7nm process" is clearly in error.
 
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JoeRambo

Golden Member
Jun 13, 2013
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1). TSMC hasn't used "nm" in their node names since 16nm/12nm
2). Intel had a 7hm process and renamed it to Intel 4

Anyone referring to Intel 7 as a "7nm process" is clearly in error.

Semantics mostly, discussed and argued over and over again. Neither has any actual 7nm features in them and both can be called "7nm (marketing) class" processes.
What is important tho, is that Intel is back to being full node behind AMD.
 

Henry swagger

Senior member
Feb 9, 2022
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Semantics mostly, discussed and argued over and over again. Neither has any actual 7nm features in them and both can be called "7nm (marketing) class" processes.
What is important tho, is that Intel is back to being full node behind AMD.
Polly pitch was the real nm number.. i judge a node by density and polly pitch
 

Exist50

Platinum Member
Aug 18, 2016
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Looks like the images got nuked off of twitter, but there're still all available here.


One would hope that, if nothing else, this would dispel some silly "predictions" about peak clocks.
 
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lightisgood

Member
May 27, 2022
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In theory, Intel must use EUV on M0 (and FEOL) only.
Other metal layer could be dealt with by SADP or single patterning.
This fact is very significant in yield / throughput.

Intel 4/3 & TSMC N3(N5?) combination might get back INTC's leadership.
I'm sure, IDM 2.0 is correct strategy.
 

Henry swagger

Senior member
Feb 9, 2022
363
236
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In theory, Intel must use EUV on M0 (and FEOL) only.
Other metal layer could be dealt with by SADP or single patterning.
This fact is very significant in yield / throughput.

Intel 4/3 & TSMC N3(N5?) combination might get back INTC's leadership.
I'm sure, IDM 2.0 is correct strategy.
Intel 4 has the highest density in the industry.. should be good for many years like 14nm