AMD, since it has a separate IO die that contains all the memory channels and PCIe, doesn’t always have to use all 8 chiplets in every SKU. In non-stacked
Milan parts, L3 can vary from 64MB to 256MB, which hints at fewer chiplets being used at times. For example the 32/64
7513 part has 128MB L3. This part can be made with 4 fully functional chiplets, or with 5 to 8 chiplets with varying numbers of core and L3 slices disabled. This gave AMD (starting with EPYC2) a lot of freedom, and it was a very frugal and brilliant design given their financial constraints.