A 5950X @4.5 scores above 30kA nearly 29K score in R23 for the 5950X requires an overclock to 4.5 GHz all core. I'd be surprised if AMD is claiming the 40+% over that, more likely it's against a stock 5950X that scores in the 25.5K range.
A 5950X @4.5 scores above 30kA nearly 29K score in R23 for the 5950X requires an overclock to 4.5 GHz all core. I'd be surprised if AMD is claiming the 40+% over that, more likely it's against a stock 5950X that scores in the 25.5K range.
ADL P-core doesn't consume only 15W per core to achieve 5GHz.I think a lot depends on what clocks they can achieve in 10W per core region with CB23 load. It takes Intel ~15W per core to achieve 5Ghz on P cores, so i would not be surprised that AMD can hit 5Ghz on new process @ 10W.
Bodes well for me anyway, as i run 3950/5950 at fixed clocks and undervolts.
You didn't mention, that you were talking about an undervolted ADL and HT was off.Blender is a quite a bit different workload than CB23, more demanding. Still stock CB23 would not use 15W for 5Ghz either.
I am using my own undervolted and fixed @5ghz cpu. Running @ 5Ghz CB23 it is 130W without HT. Would be more in Blender i believe and HT would add some more. But still in ballpark of 15W per core for 5Ghz.
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My fault, sorry if that made an impression that out of box 12900K can somehow hit 5Ghz on P cores on such low power.You didn't mention, that you were talking about an undervolted ADL and HT was off.
Pretty sure he's wrong about Foveros Omni and N3.Semianalysis thinks the chiplet on the right belongs to the GPU. Great analysis by the way from them.
The title of the article is a pretty big hint. I'll leave it at that.https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?
It would have to be SPR, MTL, or GNR, presumably, not that that narrows it down much. Though if it's a) true, and b) SPR again, well, clearly Intel's execution has yet to even slightly recover.https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?
https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?
Delaying Sapphire Rapids is not a right thing.....and is disasterous...... I have to wonder if it's Raptorlakewe feel Intel is unquestionably doing the right thing here.
Charlie doesn't care about RPL, at least not to a degree to call this a major story.Delaying Sapphire Rapids is not a right thing.....and is disasterous...... I have to wonder if it's Raptorlake
Tags: bug, CPU, delay, Intel, SemiAccurate, serious, they are doing right, this sucksSounds like GPU.
Sounds like Sapphire Rapids, given the CPU tag, and “delays again” in the title. I guess it requires another stepping to fix a serious bug.Tags: bug, CPU, delay, Intel, SemiAccurate, serious, they are doing right, this sucks
The bug may affect only the SPR Xeon scalable (non monolithic), and not SPR Xeon-W (monolithic). Maybe it’s related to Optane or CXL or something that‘s not supported on Xeon-WIf its SPR, then its disappointing. Just yesterday i read, granted on WCCF, that SPR Xeons-W are coming in October, including that mainstream ”hedt” line-up topping at those rumorex 24 cores. So maybe theyre not really and its just another unfounded rumor.
Xeon-W Sapphire Rapids will allegedly have two dead tiles and two 12c tiles. If I recall correctly? Anyway it should be much easier for Intel to ship this product than a full server-class Sapphire Rapids.If its SPR, then its disappointing. Just yesterday i read, granted on WCCF, that SPR Xeons-W are coming in October, including that mainstream ”hedt” line-up topping at those rumorex 24 cores. So maybe theyre not really and its just another unfounded rumor.
What makes you think the Xeon-W will be monolithic?The bug may affect only the SPR Xeon scalable (non monolithic), and not SPR Xeon-W (monolithic). Maybe it’s related to Optane or CXL or something that‘s not supported on Xeon-W
That's odd. My 3900X @ default clocks outperforms most other 3900X results out there in CBR23 (mine just got a 19423 in a throwaway run with browser still open). I always chalked it up to the memory tune.Actually not really. The only bearing memory has on a 5950x for CB R23 is higher FCLK/memory eats into the limited power budget and forces lower clocks. At stock jedec 2133/1066 FCLK I will see slightly higher all core boost and around 26.5k scores. At my preferred 3800/1900 FCLK I get lower boost with stock power limit and see ~25,500.
It's entirely limited by power, and no other reason on a CPU stock config.
This is probably the most likely scenario, but why there would need to be those dead tiles again? Why not just 2 12 core tiles connected via that EMIB bridge?Xeon-W Sapphire Rapids will allegedly have two dead tiles and two 12c tiles. If I recall correctly? Anyway it should be much easier for Intel to ship this product than a full server-class Sapphire Rapids.
There was MLID rumor this will be the case. We shall see.What makes you think the Xeon-W will be monolithic?
Someone explained it, it went in one eye and out the other (?!?!) so sorry, I just don't remember.This is probably the most likely scenario, but why there would need to be those dead tiles again? Why not just 2 12 core tiles connected via that EMIB bridge?
Um, well, uh . . . maybe?Surely they can produce fully functional 15 core tile?
The max 60 (15x4) core SPR chip is made with four XCC chiplets. In this design, a significant amount of space is used on two edges of these chiplets to bridge (using EMIB) the mesh from one XCC chiplet to the next.What makes you think the Xeon-W will be monolithic?
There definately will be sub-8 core per chiplet Metal Xeons.How do you think they will make lower core count (say 28) chips? Definitely not by disabling half the cores on XCC chiplets; that’s too wasteful.
Volume of Xeon-W isn't much. Partially busted EMIB models should be enough to satisfy the demand.Also not by using 4 smaller chiplets; the area dedicated to EMIB will dominate even more. It would be much more cost efficient (total silicon used, and yield) to make smaller MCC monolithic chips at the lower end. And, these can also be repurposed for Xeon-W.
Correct, some misguided folks here think that Intel will go to the trouble of making a Single 24C/48T Monolithic dieXeon-W Sapphire Rapids will allegedly have two dead tiles and two 12c tiles. If I recall correctly? Anyway it should be much easier for Intel to ship this product than a full server-class Sapphire Rapids.
A 24C/48T Sapphire Rapids CPU has been listed by YuuKi_AnS which is a good sourceBut it’s also possible that SPR won’t offer low core count chips (say below 40), and that slack is picked up by IceLake. We have to wait and see…
At that point, it’s better to make a monolithic chip -- less silicon used, simpler design, and better yield.There definately will be sub-8 core chiplet Metal Xeons.
Yes, but the volume of low core count chips is huge. And those chips are being repurposed for Xeon-W.Volume of Xeon-W isn't much. Partially busted EMIB models should be enough to satisfy the demand.
But you need the full 8 channels for the Metals. This alleged 24 core monolithic part is quad channel.At that point, it’s better to make a monolithic chip -- less silicon used, simpler design, and better yield.