Discussion Intel current and future Lakes & Rapids thread

[MarkPost]

A nearly 29K score in R23 for the 5950X requires an overclock to 4.5 GHz all core. I'd be surprised if AMD is claiming the 40+% over that, more likely it's against a stock 5950X that scores in the 25.5K range.

A 5950X @4.5 scores above 30k

 

[TESKATLIPOKA]

I think a lot depends on what clocks they can achieve in 10W per core region with CB23 load. It takes Intel ~15W per core to achieve 5Ghz on P cores, so i would not be surprised that AMD can hit 5Ghz on new process @ 10W.
Bodes well for me anyway, as i run 3950/5950 at fixed clocks and undervolts.

ADL P-core doesn't consume only 15W per core to achieve 5GHz.
Blender

That's >30W per core for less than 5GHz.

~15W per core means only 4250MHz.

 

[JoeRambo]

Blender is a quite a bit different workload than CB23, more demanding. Still stock CB23 would not use 15W for 5Ghz either.

I am using my own undervolted and fixed @5ghz cpu. Running @ 5Ghz CB23 it is 130W without HT. Would be more in Blender i believe and HT would add some more. But still in ballpark of 15W per core for 5Ghz.
Stock settings and 12900K SKU never really made sense, between 125W and 283W there is 7% gain in score for blender, awesome deal.
And there is another interesting points on that graph: 65W 8+8 scores the same as 125W 8+0. 125W 8+8 is 33% better than both of those. 8+16 would go ballistic with score already, beating that 283W abomination @ 125W.

 

[TESKATLIPOKA]

Blender is a quite a bit different workload than CB23, more demanding. Still stock CB23 would not use 15W for 5Ghz either.

I am using my own undervolted and fixed @5ghz cpu. Running @ 5Ghz CB23 it is 130W without HT. Would be more in Blender i believe and HT would add some more. But still in ballpark of 15W per core for 5Ghz.
.....

You didn't mention, that you were talking about an undervolted ADL and HT was off.

 

[JoeRambo]

You didn't mention, that you were talking about an undervolted ADL and HT was off.

My fault, sorry if that made an impression that out of box 12900K can somehow hit 5Ghz on P cores on such low power.

That is simply not happening cause Intel was not caring about efficiency at those operating points for this SKU.
During manufacture of chip several things happen that ruin any illusion of operating properly at lowest possible power at any given point:

1) Each core is characterized and has it's v/f curve determined. So in our 5Ghz case what matters is last three points. 42x, 48x and 53x ( later mfg date 12900K will have 52x instead of 53x as so called "OC ratio" ).
2) Each cores values are written to chip and are then used to interpolate voltage required at any given operational point.

During operation, largest requested value is selected out of active cores, so if a chip has a lemon core that cannot do 53x without 0.05V more than best core ( but would work perfectly @ 5ghz at same low voltage as others) => bad for you.

So at any point other than 48x or 53x we are at huge disadvantage already and 50x is esp hurt since it is far away from 53x, and yet quality of chip at peak frequency determined how much power it will eat at lower freq.

Later on after this voltage is decided by interpolation @50x, the usual guard bands for AVX, for motherboard VRM quality and so on are added and we arrive at ridiculous voltage that has nothing to do what this particular chip would really need on this frequency. Then feedback loop of TVB happens where chips voltage gets corrected by raising temperature to keep it stable.
Power usage goes ballistic, freq is dropped, but temps are stuck high, so is TVB correction, further inefficient points are selected and chip will eventually settle down on 48-49 if load is low enough or drop down to 42-43 if it is brutal as shown by ComputerBase in Your article.

Back to our original discussion -> 5ghz is just a point I happen to be running, it is in no way in most efficient part of operation for GC core in 4-5ghz range. But ballpark figure is that Intel would need ~15W @ 5Ghz to run CB23 for GC cores and we will see how much AMD will need. I am running 5950x 4.4ghz in low 1.1x regime, so we'll see how 7950x will do.

 

[Tarkin77]

https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?

 

[mikk]

Is this better?

View attachment 61429

Semianalysis thinks the chiplet on the right belongs to the GPU. Great analysis by the way from them.

https://twitter.com/i/web/status/1529866136103399424

 

[Exist50]

Semianalysis thinks the chiplet on the right belongs to the GPU. Great analysis by the way from them.

https://twitter.com/i/web/status/1529866136103399424

Pretty sure he's wrong about Foveros Omni and N3.

 

[Saylick]

https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?

The title of the article is a pretty big hint. I'll leave it at that.

 

[Exist50]

https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?

It would have to be SPR, MTL, or GNR, presumably, not that that narrows it down much. Though if it's a) true, and b) SPR again, well, clearly Intel's execution has yet to even slightly recover.

 

[deasd]

https://semiaccurate.com/2022/05/26/intel-delays-a-major-product-again/ and what could that be?

we feel Intel is unquestionably doing the right thing here.

Delaying Sapphire Rapids is not a right thing.....and is disasterous...... I have to wonder if it's Raptorlake

 

[coercitiv]

Delaying Sapphire Rapids is not a right thing.....and is disasterous...... I have to wonder if it's Raptorlake

Charlie doesn't care about RPL, at least not to a degree to call this a major story.

 

[JasonLD]

Sounds like GPU.

 

[Tarkin77]

Sounds like GPU.

Tags: bug, CPU, delay, Intel, SemiAccurate, serious, they are doing right, this sucks

 

[ashFTW]

Tags: bug, CPU, delay, Intel, SemiAccurate, serious, they are doing right, this sucks

Sounds like Sapphire Rapids, given the CPU tag, and “delays again” in the title. I guess it requires another stepping to fix a serious bug.

 

[Timmah!]

If its SPR, then its disappointing. Just yesterday i read, granted on WCCF, that SPR Xeons-W are coming in October, including that mainstream ”hedt” line-up topping at those rumorex 24 cores. So maybe theyre not really and its just another unfounded rumor.

 

[ashFTW]

If its SPR, then its disappointing. Just yesterday i read, granted on WCCF, that SPR Xeons-W are coming in October, including that mainstream ”hedt” line-up topping at those rumorex 24 cores. So maybe theyre not really and its just another unfounded rumor.

The bug may affect only the SPR Xeon scalable (non monolithic), and not SPR Xeon-W (monolithic). Maybe it’s related to Optane or CXL or something that‘s not supported on Xeon-W

 

[DrMrLordX]

If its SPR, then its disappointing. Just yesterday i read, granted on WCCF, that SPR Xeons-W are coming in October, including that mainstream ”hedt” line-up topping at those rumorex 24 cores. So maybe theyre not really and its just another unfounded rumor.

Xeon-W Sapphire Rapids will allegedly have two dead tiles and two 12c tiles. If I recall correctly? Anyway it should be much easier for Intel to ship this product than a full server-class Sapphire Rapids.

The bug may affect only the SPR Xeon scalable (non monolithic), and not SPR Xeon-W (monolithic). Maybe it’s related to Optane or CXL or something that‘s not supported on Xeon-W

What makes you think the Xeon-W will be monolithic?

Actually not really. The only bearing memory has on a 5950x for CB R23 is higher FCLK/memory eats into the limited power budget and forces lower clocks. At stock jedec 2133/1066 FCLK I will see slightly higher all core boost and around 26.5k scores. At my preferred 3800/1900 FCLK I get lower boost with stock power limit and see ~25,500.

It's entirely limited by power, and no other reason on a CPU stock config.

That's odd. My 3900X @ default clocks outperforms most other 3900X results out there in CBR23 (mine just got a 19423 in a throwaway run with browser still open). I always chalked it up to the memory tune.

Regardless, it looks like the power numbers on that Raphael 16c demo are now up in the air, so comparing it to hypothetical upcoming Raptor Lake 8+16 is now even less fruitful. Even if it is 42% faster than a 5950X, we don't know at what power (it's less than 230W, that's all we know).

 

[Timmah!]

Xeon-W Sapphire Rapids will allegedly have two dead tiles and two 12c tiles. If I recall correctly? Anyway it should be much easier for Intel to ship this product than a full server-class Sapphire Rapids.

This is probably the most likely scenario, but why there would need to be those dead tiles again? Why not just 2 12 core tiles connected via that EMIB bridge?

What makes you think the Xeon-W will be monolithic?

There was MLID rumor this will be the case. We shall see.

Personally i found both options (2 x 12C tiles) and monolithic 24 core rather weird. If one tile is 15 core, why are they capping it at 12 core and thus 24 core for entire SKU? Surely they can produce fully functional 15 core tile? I find it difficult to believe, the top "product" would not have 2 uncut dies. Was it not the whole purpose moving to this tile solution to improve the yields, so they can produce higher core-count CPUs?

The monolithic 24 core CPU then, unless again thats cut-down, is rather weird number, as it does not make much sense, if you are trying to figure out the "grid" configuration of the cores.

All of it sounds to be somewhat bogus.

 

[DrMrLordX]

This is probably the most likely scenario, but why there would need to be those dead tiles again? Why not just 2 12 core tiles connected via that EMIB bridge?

Someone explained it, it went in one eye and out the other (?!?!) so sorry, I just don't remember.

Surely they can produce fully functional 15 core tile?

Um, well, uh . . . maybe?

When was the last time Intel went over 8c Cove on any of their 10nm nodes? IceLake-SP. Look at how THAT turned out. Woof.

 

[ashFTW]

What makes you think the Xeon-W will be monolithic?

The max 60 (15x4) core SPR chip is made with four XCC chiplets. In this design, a significant amount of space is used on two edges of these chiplets to bridge (using EMIB) the mesh from one XCC chiplet to the next.

How do you think they will make lower core count (say 28) chips? Definitely not by disabling half the cores on XCC chiplets; that’s too wasteful. Also not by using 4 smaller chiplets; the area dedicated to EMIB will dominate even more. It would be much more cost efficient (total silicon used, and yield) to make smaller MCC monolithic chips at the lower end. And, these can also be repurposed for Xeon-W.

But it’s also possible that SPR won’t offer low core count chips (say below 40), and that slack is picked up by IceLake. We have to wait and see…

 

[jpiniero]

How do you think they will make lower core count (say 28) chips? Definitely not by disabling half the cores on XCC chiplets; that’s too wasteful.

There definately will be sub-8 core per chiplet Metal Xeons.

Also not by using 4 smaller chiplets; the area dedicated to EMIB will dominate even more. It would be much more cost efficient (total silicon used, and yield) to make smaller MCC monolithic chips at the lower end. And, these can also be repurposed for Xeon-W.

Volume of Xeon-W isn't much. Partially busted EMIB models should be enough to satisfy the demand.

 

[nicalandia]

Xeon-W Sapphire Rapids will allegedly have two dead tiles and two 12c tiles. If I recall correctly? Anyway it should be much easier for Intel to ship this product than a full server-class Sapphire Rapids.

Correct, some misguided folks here think that Intel will go to the trouble of making a Single 24C/48T Monolithic die

This is what I predict it will look with two 12 Core tiles and two dummy Silicon Tiles for suport

But it’s also possible that SPR won’t offer low core count chips (say below 40), and that slack is picked up by IceLake. We have to wait and see…

A 24C/48T Sapphire Rapids CPU has been listed by YuuKi_AnS which is a good source

 

[ashFTW]

There definately will be sub-8 core chiplet Metal Xeons.

At that point, it’s better to make a monolithic chip -- less silicon used, simpler design, and better yield.

Volume of Xeon-W isn't much. Partially busted EMIB models should be enough to satisfy the demand.

Yes, but the volume of low core count chips is huge. And those chips are being repurposed for Xeon-W.

 

[jpiniero]

At that point, it’s better to make a monolithic chip -- less silicon used, simpler design, and better yield.

But you need the full 8 channels for the Metals. This alleged 24 core monolithic part is quad channel.