For Servers? The same way AMD has 8C/16T EPYC processors offers 8 Channel Memory, by enabling just two cores per CCD. In the Sapphire Rapids case it will be 6 Cores per tile.
For HEDT parts those 24C/48T parts will only have two active tiles so you can only expect Quad Channel
AMD, since it has a separate IO die that contains all the memory channels and PCIe, doesn’t always have to use all 8 chiplets in every SKU. In non-stacked
Milan parts, L3 can vary from 64MB to 256MB, which hints at fewer chiplets being used at times. For example the 32/64
7513 part has 128MB L3. This part can be made with 4 fully functional chiplets, or with 5 to 8 chiplets with varying numbers of core and L3 slices disabled. This gave AMD (starting with EPYC2) a lot of freedom, and it was a very frugal and brilliant design given their financial constraints.
SPR on the other hand, since it only has a 1/4th subset of memory controllers, PCIe, CXL, UPI on each of the tiles, they cannot make a chip with full IO unless all 4 chiplets are used. That makes sense for large core count parts. For smaller core counts it’s much cheaper to make monolithic. It would be a disaster if they had to use 1600 mm2 silicon (not counting the EMIB tiles) for every SKU, some of them may even go as low as 8/12/16 cores. Keeping the 4 chiplet design for lower core count also doesn’t make sense, because if you decide to make smaller “1/4th split chiplets”, you might as well make a monolithic which will be far cheaper to make. Intel in the past has made several different size Xeon chips to address the core count range — XCC, MCC, LCC. So they are likely to make several size chips; they do not have the financial constraints to only make one tile (and it’s mirror) for SPR.
In conclusion, we will see the 4 chiplet SPR design only for high core counts. There will be up to two (MCC and LCC, using the older terminology) monolithic die for smaller core counts. These monolithic die will be repurposed for Xeon-W. In the future, maybe with Granite Rapids, Intel will start making disaggregated Xeon chips. But even then they will make different size CPU tiles with varying number of cores. Here Foveros Omni starts to make sense with different size CPU tiles “hanging” off one of the edges, and their connectivity to other chips will be in the ”non-hanging part“, which all sized tiles will contain.