Discussion Intel current and future Lakes & Rapids thread

[ashFTW]

There definately will be sub-8 core chiplet Metal Xeons.

At that point, it’s better to make a monolithic chip -- less silicon used, simpler design, and better yield.

Volume of Xeon-W isn't much. Partially busted EMIB models should be enough to satisfy the demand.

Yes, but the volume of low core count chips is huge. And those chips are being repurposed for Xeon-W.

 

[jpiniero]

At that point, it’s better to make a monolithic chip -- less silicon used, simpler design, and better yield.

But you need the full 8 channels for the Metals. This alleged 24 core monolithic part is quad channel.

 

[ashFTW]

Correct, some misguided folks here think that Intel will go to the trouble of making a Single 24C/48T Monolithic die

This is what I predict it will look with two 12 Core tiles and two dummy Silicon Tiles for suport

How do you see Intel making a 24 core SPR server chip with 8 channel memory? You either use 4 XCC chiplets that are severely disabled, or you build a monolithic MCC chip as well. I believe MCC monolithic is a better option.

 

[ashFTW]

But you need the full 8 channels for the Metals. This alleged 24 core monolithic part is quad channel.

You build 8 channel MCC chip, and only use 4 when repurposing it as Xeon-W.

 

[ashFTW]

A 24C/48T Sapphire Rapids CPU has been listed by YuuKi_AnS which is a good source

Well in that case, I’m sure Intel will make a monolithic MCC chip for all the reasons I have given above. The 4 chiplet design only makes sense for high core count chips.

 

[nicalandia]

Well in that case, I’m sure Intel will make a monolithic MCC chip for all the reasons I have given above. The 4 chiplet design only makes sense for high core count chips.

Another Misguided Soul I see.

Look the 24C/48T HEDT parts will have 45 MiB L3 Cache and Quad Channel memory.. What do you think Intel is going to do with bottom of the Barrel Compute Tiles?

 

[Timmah!]

Another Misguided Soul I see.

Look the 24C/48T HEDT parts will have 45 MiB L3 Cache and Quad Channel memory.. What do you think Intel is going to do with bottom of the Barrel Compute Tiles?

Seems you 2 need to make this a stake I am honestly curious who will turn to be right.

 

[ashFTW]

Another Misguided Soul I see.

Look the 24C/48T HEDT parts will have 45 MiB L3 Cache and Quad Channel memory.. What do you think Intel is going to do with bottom of the Barrel Compute Tiles?

Please guide me, since I’m so misguided: How do you think Intel will make the 24/48 CPU that you pointed to earlier with 8 channel memory?

 

[jpiniero]

How do you see Intel making a 24 core SPR server chip with 8 channel memory? You either use 4 XCC chiplets that are severely disabled,

Given that they keep delaying SPR, presumably because of yields, there's likely to be plenty of those. A theoretical monothlic 24 core SPR would be rather big for 10 nm, so you'd be cutting down anyway for the most part.

 

[ashFTW]

Given that they keep delaying SPR, presumably because of yields, there's likely to be plenty of those. A theoretical monothlic 24 core SPR would be rather big for 10 nm, so you'd be cutting down anyway for the most part.

IceLake XCC is bigger, and the 10nm process has vastly improved since. ADL-S is 220 mm2, and they have no problems manufacturing that, both in terms of capacity and yield. SPR tile is less than double at 400mm2.

 

[Schmide]

intel makes meshyring 8 10 12 14 28 56 112

 

[jpiniero]

IceLake XCC is bigger

Volume of that is probably very tiny considering any customer considering any XCC model is buying Epyc. I don't know how big a 24 SPR core part would be but I'll guess it'd be about the XCC die size.

ADL-S is 220 mm2, and they have no problems manufacturing that, both in terms of capacity and yield.

Except the main seller is the 12400, which has "half" the cores enabled and almost half the cache enabled. They could cut even further later and throw it into the i3 range if need be.

 

[Timmah!]

Volume of that is probably very tiny considering any customer considering any XCC model is buying Epyc. I don't know how big a 24 SPR core part would be but I'll guess it'd be about the XCC die size.

Wasnt IceLake XCC like 40 cores? Is Golden Cove core that much bigger to make up for 18 less cores (assuming that 24 is full fat die)?
Additionally, is 10nm IceLake the exact same process as the 10nm Alder Lake/SPR?

 

[nicalandia]

Please guide me, since I’m so misguided: How do you think Intel will make the 24/48 CPU that you pointed to earlier with 8 channel memory?

For Servers? The same way AMD has 8C/16T EPYC processors offers 8 Channel Memory, by enabling just two cores per CCD. In the Sapphire Rapids case it will be 6 Cores per tile.

For HEDT parts those 24C/48T parts will only have two active tiles so you can only expect Quad Channel

 

[jpiniero]

Wasnt IceLake XCC like 40 cores? Is Golden Cove core that much bigger to make up for 18 less cores (assuming that 24 is full fat die)?
Additionally, is 10nm IceLake the exact same process as the 10nm Alder Lake/SPR?

40 yes. You do have all the additional IO that SPR has too, even excluding the EMIB. But I haven't seriously looked into how big it would be.

Edit: And Icelake-W is still MIA it looks. OEMs are selling Alder Lake with ECC enabled.

 

[igor_kavinski]

AMD does not have an answer to Intel at $99 as far as gaming is concerned. Pretty impressive that the i3-12100 is able to scale so well with high performance memory. Question is, is the i3-12100 with expensive memory better than the i5-12400 with normal memory?

 

[nicalandia]

And Icelake-W is still MIA it looks.

It's not MIA, but when your product is struggling against Zen2, Intel will not promoted these as UHEDT Monsters.

 

[ashFTW]

For Servers? The same way AMD has 8C/16T EPYC processors offers 8 Channel Memory, by enabling just two cores per CCD. In the Sapphire Rapids case it will be 6 Cores per tile.

For HEDT parts those 24C/48T parts will only have two active tiles so you can only expect Quad Channel

AMD, since it has a separate IO die that contains all the memory channels and PCIe, doesn’t always have to use all 8 chiplets in every SKU. In non-stacked Milan parts, L3 can vary from 64MB to 256MB, which hints at fewer chiplets being used at times. For example the 32/64 7513 part has 128MB L3. This part can be made with 4 fully functional chiplets, or with 5 to 8 chiplets with varying numbers of core and L3 slices disabled. This gave AMD (starting with EPYC2) a lot of freedom, and it was a very frugal and brilliant design given their financial constraints.

SPR on the other hand, since it only has a 1/4th subset of memory controllers, PCIe, CXL, UPI on each of the tiles, they cannot make a chip with full IO unless all 4 chiplets are used. That makes sense for large core count parts. For smaller core counts it’s much cheaper to make monolithic. It would be a disaster if they had to use 1600 mm2 silicon (not counting the EMIB tiles) for every SKU, some of them may even go as low as 8/12/16 cores. Keeping the 4 chiplet design for lower core count also doesn’t make sense, because if you decide to make smaller “1/4th split chiplets”, you might as well make a monolithic which will be far cheaper to make. Intel in the past has made several different size Xeon chips to address the core count range — XCC, MCC, LCC. So they are likely to make several size chips; they do not have the financial constraints to only make one tile (and it’s mirror) for SPR.

In conclusion, we will see the 4 chiplet SPR design only for high core counts. There will be up to two (MCC and LCC, using the older terminology) monolithic die for smaller core counts. These monolithic die will be repurposed for Xeon-W. In the future, maybe with Granite Rapids, Intel will start making disaggregated Xeon chips. But even then they will make different size CPU tiles with varying number of cores. Here Foveros Omni starts to make sense with different size CPU tiles “hanging” off one of the edges, and their connectivity to other chips will be in the ”non-hanging part“, which all sized tiles will contain.

 

[Timmah!]

What do you reckon clocks would be on that hypothetical 24C chip? I mean, single core or bunch of them will probably be able to hit 5GHz+ like regular Alder Lake GC cores... but i think all-core turbo. How much power do 8GC cores in Alder Lake draw at 4GHz? And what about 4,5GHz?

 

[DrMrLordX]

AMD does not have an answer to Intel at $99 as far as gaming is concerned.

They don't have anything at $99. Not really.

How do you think they will make lower core count (say 28) chips? Definitely not by disabling half the cores on XCC chiplets; that’s too wasteful.

Unless . . .

It would be much more cost efficient (total silicon used, and yield) to make smaller MCC monolithic chips at the lower end.

What if they can't? What if the most cores they can yield on one tile is 15c, and they're struggling even to hit that target?

 

[ashFTW]

What if they can't? What if the most cores they can yield on one tile is 15c, and they're struggling even to hit that target?

You know there is a monolithic 40 core IceLake Xeon already on 10nm, right? And according to the last earnings call, it’s in high volume manufacturing, selling 3M units last quarter. Of course, Intel doesn’t share what portion of that was XCC. At this point 10nm (Intel 10, Intel 7) is very healthy. The focus has now shifted to Intel 4/3 and Intel 20A/18A.

 

[DrMrLordX]

You know there is 40 core IceLake Xeon already on 10nm, right?

1). That's 10nm+
2). Different core
3). Different I/O layout

The proof is in the pudding. Sapphire Rapid still isn't out yet. They may have a lot of failed tiles, though.

 

[lightisgood]

I guess that MCC "24 Core Tile" was prepared for Birch Stream-AP LGA7529, DDR5-16ch, up-to-96cores and zen4-epyc competitor.

But probably now, it replaced by Emerald rapids-AP or Granite.

 

[Exist50]

1). That's 10nm+
2). Different core
3). Different I/O layout

The proof is in the pudding. Sapphire Rapid still isn't out yet. They may have a lot of failed tiles, though.

There are other reasons for a product to be delayed than yields...

 

[ashFTW]

I guess that MCC "24 Core Tile" was prepared for Birch Stream-AP LGA7529, DDR5-16ch, up-to-96cores and zen4-epyc competitor.

But probably now, it replaced by Emerald rapids-AP or Granite.

I think Emerald Rapids will use the same system design as SPR, with updated core and uncore. There will be an additional row/col of cores in the chiplets to add up to 4 or 5 cores per chiplet, for a total of 16 to 20 additional cores per chip compared to SPR.