Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

but they imply in their rumor or leak whatever it is, there is another SPR die, one not meant to be used as a tile, but regular monolithic chip. Surely thats not impossible?

You would think if they were capable of making a Larger compute tile with 24 cores that had quad channel memory, they would use it on the Top of the line Sapphire Rapids and charge $20,000 for it. That would give them 96C/192T with 16 memory Channel to combat the Zen4 Monster that is about to be released.

But instead they will be releasing a 56C/112T part by the end of 2022 or early 2023 just to get mauled by Genoa and Bergamo?

 

[jpiniero]

but they imply in their rumor or leak whatever it is, there is another SPR die, one not meant to be used as a tile, but regular monolithic chip. Surely thats not impossible?

Not impossible. It would be super dumb. Intel is that dumb, but I would just chalk it up to MLID being MLID.

 

[Timmah!]

You would think if they were capable of making a Larger compute tile with 24 cores that had quad channel memory, they would use it on the Top of the line Sapphire Rapids and charge $20,000 for it. That would give them 96C/192T with 16 memory Channel to combat the Zen4 Monster that is about to be released.

But instead they will be releasing a 56C/112T part by the end of 2022 or early 2023 just to get mauled by Genoa and Bergamo?

I dont know, perhaps they are not making 4x24c part, cause it would be too power-hungry, or because it would not physically fit into that 4677 socket?

they had 40 core monolithic chips before, if they chose to make their SPR tiles only 15 cores, clearly the reason is not that they could not do more, but because they chose not to.

 

[nicalandia]

I dont know, perhaps they are not making 4x24c part, cause it would be too power-hungry, or because it would not physically fit into that 4677 socket?

The leak suggest that it's going to use the same 4677 Socket

they had 40 core monolithic chips before, if they chose to make their SPR tiles only 15 cores, clearly the reason is not that they could not do more, but because they chose not to.

The reason they are not doing that anymore is due to better yields with Chiplets/Tiles which means more products and more revenue.

 

[Timmah!]

Not impossible. It would be super dumb. Intel is that dumb, but I would just chalk it up to MLID being MLID.

Well, i would not be surprised if he pulled the whole rumor out of his back part, but i was surprised how swiftly nicalandia dismissed it.
anyway, why would it be superdumb? Wouldnt single 24 core chip be cheaper than those 2 emib dies with all the advanced packaging?

 

[ashFTW]

Not a chance of being a single Monolith chunk of silicon, it's going to be like this, SPR is limited by 2 channels per compute tile(So four channel will be two compute tiles).. The "Monolithic" term is used as "Software Monolithic"

View attachment 61185

The two tiles as depicted above can’t even communicate with each other using EMIB.

 

[Timmah!]

The leak suggest that it's going to use the same 4677 Socket

Well, i know. and hypothetical 96 core part might not fit it. Thats why they are not making it, and only 56 core part.

 

[nicalandia]

The two tiles as depicted above can’t even communicate with each other using EMIB.

Why not? As far as I am aware the EMIB does not require that All tiles to be active.

The depiction I made was taking into consideration an even heat dissipation.

Would this work?

 

[ashFTW]

Well, i know. and hypothetical 96 core part might not fit it. Thats why they are not making it, and only 56 core part.

Given that there is space in there for 4 HBM2 stacks, I’m sure at least one more row/column of cores can fit per tile adding 4x4 cores per socket. that would be max 76 cores. Don’t know if there is enough space for an additional row/column.



The rumored SPR-W monolithic die could be a 5x5 matrix, which comes to precisely 24 cores.

 

[ashFTW]

Given that there is space in there for 4 HBM2 stacks, I’m sure at least one more row/column of cores can fit per tile adding 4x4 cores per socket. that would be max 76 cores. Don’t know if there is enough space for an additional row/column.

View attachment 61187

The rumored SPR-W monolithic die could be a 5x5 matrix, which comes to precisely 24 cores.

4 of these could be the biggest Emerald Rapids configuration with 96 cores.

 

[ashFTW]

Why not? As far as I am aware the EMIB does not require that All tiles to be active.

The depiction I made was taking into consideration an even heat dissipation.

Would this work?

View attachment 61188

Yes, this should work.

 

[Timmah!]

Given that there is space in there for 4 HBM2 stacks, I’m sure at least one more row/column of cores can fit per tile adding 4x4 cores per socket. that would be max 76 cores. Don’t know if there is enough space for an additional row/column.

View attachment 61187

The rumored SPR-W monolithic die could be a 5x5 matrix, which comes to precisely 24 cores.

You think that single memory control tile would be enough for 24 cores chip? If 18 core skylake had 2…

 

[jpiniero]

Well, i would not be surprised if he pulled the whole rumor out of his back part, but i was surprised how swiftly nicalandia dismissed it.
anyway, why would it be superdumb? Wouldnt single 24 core chip be cheaper than those 2 emib dies with all the advanced packaging?

Design costs and you're probably going to have plenty of chiplets with busted EMIB that you can't use for the big boy chips. You could also in theory dump those on LGA 1700.

The HEDT W volume doesn't seem that high.

 

[ashFTW]

You think that single memory control tile would be enough for 24 cores chip? If 18 core skylake had 2…

No not really, there needs to be another memory controller block for a total of 4 memory channels. But it would be frugal design practice to be able to use this tile in a 2x2 configuration as well.

 

[nicalandia]

Design costs and you're probably going to have plenty of chiplets with busted EMIB that you can't use for the big boy chips. You could also in theory dump those on LGA 1700.

The HEDT W volume doesn't seem that high.

Haven't you heard? HEDT is the most profitable of Intel's market? They will design a Huge Monolithic die just for it and leave busted/bottom of the barrel compute tiles for Sapphire Rapids Xeons..

 

[ashFTW]

Design costs and you're probably going to have plenty of chiplets with busted EMIB that you can't use for the big boy chips. You could also in theory dump those on LGA 1700.

The HEDT W volume doesn't seem that high.

The tiles with busted EMIB on one edge may be combined with another similar one to make low end bronze? Silver? SPR CPUs with half the memory channels and PCIe lanes.

 

[jpiniero]

The tiles with busted EMIB on one edge may be combined with another similar one to make low end bronze? Silver? SPR CPUs with half the memory channels and PCIe lanes.

I don't recall Intel ever having a Metal Xeon with less than the full number of memory channels. Even Bronze. It's always been the HEDT platform having half.

 

[Timmah!]

The leak suggest that it's going to use the same 4677 Socket



The reason they are not doing that anymore is due to better yields with Chiplets/Tiles which means more products and more revenue.

I know this, and clearly, since you do as well, why would you ask me why are they then not making 96 cores MCM chip, if they can? You basically answered yourself in there.

That however does not mean they might not have one additional die for lower core-count products, which would be strictly monolithic. There is no rule saying all their products from now on have to be tile-based. They only moved to tiles, because producing monolithic chips competing with 64 to 96 core EPYCs/TRs was not viable option for them. 24-core MCC though? They were producing 20+ cores chips since like Haswell-X in 2014.

 

[tomatosummit]

The tiles with busted EMIB on one edge may be combined with another similar one to make low end bronze? Silver? SPR CPUs with half the memory channels and PCIe lanes.

Problem with that is segmentation.
Be it monolithic or 2xchiplets then there's only 4 memory channels for the socket which is a marketing problem for bronze/silver xeons. AMD has a similar issue with the lowest end epycs being "designed" for only 4 memory channels but you can at least still populate the extra sockets and not just have dead dimms.

If it's a new hedt socket then I can see xeon bronze and maybe silver using the new smaller socket. Big spr is big and it's a lot of silicon to waste for 6-24core cpus for customers who only really want to keep the lights flashing on their file server.

Monolithic doesn't seem like a bad idea. People have noted how much silicon is used on the spr chips for the emib logic.
Saving space on upi, emib, coherency logic, hbm controllers and also no emib silicon itself and it's complex substrate.
I'd say it compares favourably against two tiles at these core counts.

 

[tomatosummit]

dbl post please delete

 

[ashFTW]

If it's a new hedt socket then I can see xeon bronze and maybe silver using the new smaller socket. Big spr is big and it's a lot of silicon to waste for 6-24core cpus for customers who only really want to keep the lights flashing on their file server.

Yeah I like this idea. Bronze and Silver using smaller socket should suffice most low core use cases. Low core SKUs could still be offered on the bigger socket, to cover the rest.

 

[Timmah!]

Problem with that is segmentation.
Be it monolithic or 2xchiplets then there's only 4 memory channels for the socket which is a marketing problem for bronze/silver xeons. AMD has a similar issue with the lowest end epycs being "designed" for only 4 memory channels but you can at least still populate the extra sockets and not just have dead dimms.

If it's a new hedt socket then I can see xeon bronze and maybe silver using the new smaller socket. Big spr is big and it's a lot of silicon to waste for 6-24core cpus for customers who only really want to keep the lights flashing on their file server.

Monolithic doesn't seem like a bad idea. People have noted how much silicon is used on the spr chips for the emib logic.
Saving space on upi, emib, coherency logic, hbm controllers and also no emib silicon itself and it's complex substrate.
I'd say it compares favourably against two tiles at these core counts.

Thats exactly why i think its not that far-fetched idea, even though MLID is not exactly the most trusted source.
But then again, as a simple layman, i admit to have no real clue.

 

[jpiniero]

If it's a new hedt socket then I can see xeon bronze and maybe silver using the new smaller socket. Big spr is big and it's a lot of silicon to waste for 6-24core cpus for customers who only really want to keep the lights flashing on their file server.

Which is why you would release a single tile version on LGA 1700.

 

[ashFTW]

Which is why you would release a single tile version on LGA 1700.

Yeah, makes sense for Xeon E without graphics.

Summary so far: Each 4x4 grid SPR tile has 15 cores, 32 Gen5 PCIe and 2 DDR5 memory channel support. SPR Xeon products:

1 tile: LGA1700 (Xeon E)
2 tiles or a bigger (e.g. 5x5) grid tile: HEDT socket (Xeon W)
4 tiles: LGA4677 (Xeon Scalable)

EMR will likely have support for 5x5 grid tiles. The size of the tiles and hence the number of cores is gated by the power consumption. Let’s see if by next year Intel 7 process will be further refined to address this.

 

[nicalandia]

For anyone that has recently seen this.. Don't even bother. The CPU being shown is actually a Xeon Knights Landing with HMB Memory.

Intel "Sapphire Rapids" Xeon Processor Could Feature Up To 80 Cores: New Leak

Intel's upcoming Xeon "Sapphire Rapids" enterprise processor come come with CPU core-counts as high as 80, according to the latest round of photo-leaks. An earlier article predicted the chip cram up to 56 cores alongside on-package HBM. The processor reportedly features up to 80 cores, spread...

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