Discussion Intel current and future Lakes & Rapids thread

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IntelUser2000

Elite Member
Oct 14, 2003
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I could maybe believe the number, but not the reason. Intel 3 isn't a shrink; it's just a refinement/extension. So they're not getting anything from process, and they have a new core to fit in. Honestly, I think Turin will still have the edge.

It's pretty natural for servers to get a substantial gain even for a Tick. Like even for Emerald Rapids, new cores with probably 20% higher perf/clock and 15% higher core count for 30-35% higher performance.

Yes Intel 3 isn't a shrink but a big gain nonetheless. The 18% performance gain is rather large for a refinement. They said the 10SF gains were equal to going from 14 to 14++? 18% is that kind of gain. Denser HP libraries? People are bewildered at how RibbonFET and PowerVia on 20A only offers 15% gain. Yea.

It might be their Alderlake, because Emerald Rapids will be their lowest point, as it was with Rocketlake in desktop. Things are lowest before the rise, just the natural cycle of things.
 

Exist50

Platinum Member
Aug 18, 2016
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It's pretty natural for servers to get a substantial gain even for a Tick
You're talking about nearly 3x the core count over Sapphire Rapids, which is already a ton of silicon, plus who knows what kind of additional area from +2 generations of Core, and the only thing to reign this all in, in terms of area, is a single node shrink? Like, I can believe Intel will do >120 cores, but this thing's looking to be ungodly expensive (and probably power hungry). They might well be package limited, at the end of the day.

It might be their Alderlake, because Emerald Rapids will be their lowest point, as it was with Rocketlake in desktop
I guess that's alright analogy, but I still expect Turin to be a pretty convincing win across the board. I guess Sierra Forest and "Next Forest" might help mitigate the damage from the high core count parts, but whatever the socket that comes after is (post Diamond Rapids), Intel really needs to support 256+ big cores.

Honestly, the only thing Intel looks to have going for them in the meantime is that N3 isn't in great shape. But it's still going to be much denser than Intel 3 even if PnP works out similarly, and N3E seems like a bit of a wildcard.
 

IntelUser2000

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Oct 14, 2003
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So, I am not expecting 25-30% with a new architecture now. I think we'll see Ticks that are 7-10% faster and Tocks that are 20% faster for a total of 30% per 2 years for the P cores, and 30-something % per 2 years with the E cores.

Raptorlake: 7-10%
Meteorlake: 20%
Arrowlake: 7-10%
Lunarlake: 20%

If you add another 10% with Novalake, you get to the "Up to 2x over Golden Cove" number thrown out by MLID.
 

Exist50

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Like even for Emerald Rapids, new cores with probably 20% higher perf/clock and 15% higher core count for 30-35% higher performance.
I missed this bit the first time. You're not expecting those numbers for Emerald Rapids, right?

Raptorlake: 7-10%
Meteorlake: 20%
Arrowlake: 7-10%
Lunarlake: 20%
Nah, nah. Arrow Lake and Lunar Lake use the same cores. And Lion Cove is definitely a bigger change than Redwood Cove. Though the 10-12% from the other day is concerning.

If you add another 10% with Novalake, you get to the "Up to 2x over Golden Cove" number thrown out by MLID.
That's supposedly for Royal. Very, very different.
 

DrMrLordX

Lifer
Apr 27, 2000
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@DrMrLordX FYI this is the machine Intel is currently using: TWINSCAN NXE:3600D - EUV lithography systems | ASML

1 machine produces >= 160 wph according to ASML.

160 wph fabbing what exactly?

How many EUV machines do you suppose TSMC has dedicated to N5 (and variants)? Are they getting 160 wph per machine on those nodes? I think the answer is "no", and not for want of complementary equipment to "max out" their EUV equipment.

The process is more expensive than previous generations you know? That's an industry trend.

Looking at Intel's earnings reports (vs. AMD's), it seems to be hurting Intel more than their competition.

They don't have tiles since they are not ready yet.

Sapphire Rapids is using tiles . . . granted, if the measurements are correct, the amount of silicon Intel is spending on EMIB is pretty significant on Sapphire Rapids.

Well that's because of the yields. It's actually quite amazing they are still selling tons of 14 nm Xeons.

It is, but it isn't. If Milan and IceLake-SP are sold out, what else are you going to do if you want to scale out? Sitting on a waiting list and/or just waiting for better general availability of hardware isn't always an option.
 

IntelUser2000

Elite Member
Oct 14, 2003
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I missed this bit the first time. You're not expecting those numbers for Emerald Rapids, right?

You know what, you are right. I'm confusing some code names. Emerald Rapids is after Sapphire so it should use Raptor Cove which is probably similar to RPL at 8-12%,

Nah, nah. Arrow Lake and Lunar Lake use the same cores. And Lion Cove is definitely a bigger change than Redwood Cove. Though the 10-12% from the other day is concerning.

Is that recent information? Just like we just found out Granite is Intel 3?

The original GNR should have got same core as the ones in Meteorlake which should be about 20%. 10-12% extra sounds right to me?

Arrow and Lunar using the same cores are concerning if it comes after Meteorlake which should be 20% or so. Two 10% generations? Then something like 30% jump in a single year will be needed just to get back to cadence.

Oh, you are saying Arrow has another big jump as well. Or the plans have changed.

So Nova is the big one? MLID leak about Royal Cove is that it's a series of architectures not a core. So Meteor/Arrow/Lunar all being a improved process to bring them back into competition.

The funny thing is when we were wondering how Intel will get back into competition and speed up their nodes and some were saying things won't be a linear progression(including MLID) and now they come out and the roadmap looks pretty much a linear replacement with Lunar replacing Arrow replacing Meteor replacing Raptor.
 
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Exist50

Platinum Member
Aug 18, 2016
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Is that recent information? Just like we just found out Granite is Intel 3?

The original GNR should have got same core as the ones in Meteorlake which should be about 20%. 10-12% extra sounds right to me?
I'm making some assumptions, but in theory it could have changed. I'm not working with perfect information, haha. In any case, original GNR and MTL should have both used Redwood Cove. That's the "tick", i.e. minor gains. Arrow Lake and Diamond Rapids (now seemingly renamed to Granite) should be Lion Cove. That's the "tock". My concern is that from Gelsinger's latest statements, that "tock" seemed disappointingly small. I've heard a lot of hype about Lion Cove, so that's not great.

Regarding ARL vs LNL, I am going with that old leak that showed both using Lion Cove + Skymont, which matches with my previous understanding as well. And I think there's some evidence for this, with them talking about "Lunar Lake and Beyond" as coming in "2024-". Coupled with the remarks about "Ultra Low Power Performance", I think LNL and ARL occupy non-overlapping parts of the roadmap. Maybe an optimized M part while ARL handles P and S? That would mesh with other rumors.

So Nova is the big one? MLID leak about Royal Cove is that it's a series of architectures not a core.
My understanding is that there will be a first gen "Royal Core" that I have every expectation will be extremely impressive, and which will also serve as the foundation for a new line of microarchitectures going forward. When/where that will arrive, however? Ain't got a clue. Nova Lake seems as a good a guess as any, and I think has some good political synergies, but they have a lot of flexibility, since the Core line is likely to overlap for some time. Honestly, expect things to get real weird around then. In any case, Royal is a completely separate effort from Lion Cove etc.
 

dullard

Elite Member
May 21, 2001
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The shapes for Meteorlake is way different than the actual one they have shown a little while ago.

Also it's supposed to be 384 EUs for Arrow Lake.
Yes, the Meteor Lake ones are different, which is why I spoke of Arrow Lake. These clearly are not Meteor Lake. Are you certain about 384 EUs for Arrow Lake? From what I've seen, most rumors were 320 EUs for Arrow Lake:

but 384 EUs for the discrete GPU card:
 

IntelUser2000

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Oct 14, 2003
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Yes, the Meteor Lake ones are different, which is why I spoke of Arrow Lake. These clearly are not Meteor Lake. Are you certain about 384 EUs for Arrow Lake? From what I've seen, most rumors were 320 EUs for Arrow Lake:

Yes it was from their drivers: https://videocardz.com/newz/intel-a...sti-dgpu-raptor-meteor-arrow-lunar-lake-igpus

6x4x16 = 384
 

repoman27

Senior member
Dec 17, 2018
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@DrMrLordX FYI this is the machine Intel is currently using: TWINSCAN NXE:3600D - EUV lithography systems | ASML

1 machine produces >= 160 wph according to ASML.
Thats for a single exposure. How many layers are using EUV? How many lithography steps are required for each layer? At least initially, there shouldn't be any multi-patterning for EUV layers, so it's only one exposure per step. And according to WikiChip, the plan is to use EUV for up to 12 layers for Intel 4. ASML reckons you need roughly 1 EUV system per layer for every ~45,000 wspm of fab capacity (these are older numbers but should encompass the NXE: 3400B/C scanner generations).

asml-euv-projections-capacity.png


If yields were the problem, then Intel would just launch, but with lower volume. Intel's biggest issue right now is incompetence on the design side. It's why we get absurdities like Intel saying Intel 4 will be ready by end of '22 but we won't get products till H2'23.
I believe that the original POR for Meteor Lake was PRQ and HVM in H2'22 for an initial launch in Q1'23. Their statement during the Investor Meeting 2022 session was, "Meteor Lake CPU tile production stepping tape out" in H2'22. That's essentially not even committing to PRQ by the end of Q4'22, but it also does not rule out a Q2'23 launch, which is what many folks here were expecting anyway.

Looks like they changed the Meteorlake graphics architecture from DG2 based to Battlemage DG3 based. Good thing because the architecture in DG2 isn't particularly competitive.

Some say Raja will have a hard time since he was handed the "worst" GPU architecture in the industry.
I think many folks, Ryan included, are completely misreading those slides. The architecture in the IGPs is not the same as in the dGPUs that happen to be shipping during the same timeframe. They are separate products with concurrent shipping windows. Meteor Lake (and future IGP generations) will apparently be included under the Arc brand, but MTL is Xe LPG and ARL is Xe LPG Plus, which look to be Gen12.7, or the same Xe generation as DG2/Alchemist. Battlemage is Xe2 and looks to be based on Gen12.9 ELG. Celestial should be Xe3 based on Gen13 DG3, although I'm a little confused as to the future of DG2>DG3 and ATS>JPS with the insertion of ELG and the seeming resurrection of the Arctic Sound codename.

... Where did you see that the base die is using 10nm?

I'm not necessarily convinced. The only thing that even hints at such a change is both Meteor Lake and Battlemage showing up in the same column on a diagram with time/generation as the axis. I'd still bet that it uses DG2 IP.
Intel has stated on numerous occasions at this point that MTL is using second generation Foveros with a 36 µm bump pitch, a.k.a. Intel 7 FOVEROS / 1274.FV, or in other words "10nm". Are you expecting 22nm with a 36 µm bump pitch instead?

Also, I know you believe that the base die will act as a passive interposer, but then the PCH would have to be integrated into the SOC tile for at least the mobile parts. And that smaller tile above the CPU tile, which you claim serves an I/O purpose, is only 9.0 mm x 1.9 mm = 17.1 mm². That's in the ballpark of Thunderbolt 4 redriver chips that are designed to be embedded into cable connectors. I/O and analog tends to demonstrate worse area scaling than logic or SRAM, so what node do you think that little tile is on? In what universe would it not have been more cost effective to integrate that block into one of the other tiles? I guess with Foveros you're routing signals to the base tile using TSVs as opposed to needing to stick to the perimeter for wire-bonding, but still...

Yes, the Meteor Lake ones are different, which is why I spoke of Arrow Lake. These clearly are not Meteor Lake. Are you certain about 384 EUs for Arrow Lake? From what I've seen, most rumors were 320 EUs for Arrow Lake:
but 384 EUs for the discrete GPU card:
Rumors pointed to 320 EUs, but the GPU drivers seem to show the following configurations:

gen12-hp / xe_lpg
- MTL_1x4x16
- MTL_2x4x16
- MTL_3x4x16

gen12-hp / xe_lpgplus
- ARL_6x4x16

Which would be 384 EUs total, although Intel might decline to ship a fully enabled version.
 

dullard

Elite Member
May 21, 2001
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Rumors pointed to 320 EUs, but the GPU drivers seem to show the following configurations:

gen12-hp / xe_lpg
- MTL_1x4x16
- MTL_2x4x16
- MTL_3x4x16

gen12-hp / xe_lpgplus
- ARL_6x4x16

Which would be 384 EUs total, although Intel might decline to ship a fully enabled version.
What are the chances that Intel ships two versions? One version at 5x4x16 = 320 and one version at 6x4x16? Since the GPU is a separate tile, I could see two different tiles as a theoretical possibility or I could see disabling a section for yields. It would be back like the old days where there was a UHD version and an Iris Plus version. Not that I'd complain if they were all 384 EUs. I'm one of the very few integrated graphics fans (way less power consumed, way less cost, and sufficient for my needs).
 
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yuri69

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Jul 16, 2013
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I'm making some assumptions, but in theory it could have changed. I'm not working with perfect information, haha. In any case, original GNR and MTL should have both used Redwood Cove. That's the "tick", i.e. minor gains. Arrow Lake and Diamond Rapids (now seemingly renamed to Granite) should be Lion Cove. That's the "tock". My concern is that from Gelsinger's latest statements, that "tock" seemed disappointingly small. I've heard a lot of hype about Lion Cove, so that's not great.

Regarding ARL vs LNL, I am going with that old leak that showed both using Lion Cove + Skymont, which matches with my previous understanding as well. And I think there's some evidence for this, with them talking about "Lunar Lake and Beyond" as coming in "2024-". Coupled with the remarks about "Ultra Low Power Performance", I think LNL and ARL occupy non-overlapping parts of the roadmap. Maybe an optimized M part while ARL handles P and S? That would mesh with other rumors.


My understanding is that there will be a first gen "Royal Core" that I have every expectation will be extremely impressive, and which will also serve as the foundation for a new line of microarchitectures going forward. When/where that will arrive, however? Ain't got a clue. Nova Lake seems as a good a guess as any, and I think has some good political synergies, but they have a lot of flexibility, since the Core line is likely to overlap for some time. Honestly, expect things to get real weird around then. In any case, Royal is a completely separate effort from Lion Cove etc.
Arrow and Lunar were rumored to use the same core and present a mobile/desktop lineup split. It could be true since TGL was more or less mobile only.

The Royal Core should be the long-overdue departure from the Sandy Bridge/Core base.
 

Exist50

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Their statement during the Investor Meeting 2022 session was, "Meteor Lake CPU tile production stepping tape out" in H2'22.
Did they explicitly claim the production stepping? Either way, it's the SoC that will control their schedule, and I don't expect them to PRQ till end of Q2'23 at best.

Intel has stated on numerous occasions at this point that MTL is using second generation Foveros with a 36 µm bump pitch, a.k.a. Intel 7 FOVEROS / 1274.FV, or in other words "10nm".
First part, yes. Second part, no. I don't think a passive die would fit neatly into any naming they've given, for that matter. And regardless of the naming, a passive die would be on as cheap and simple a process as possible. Way too expensive otherwise.

Also, I know you believe that the base die will act as a passive interposer, but then the PCH would have to be integrated into the SOC tile for at least the mobile parts.
Yes, exactly.

And that smaller tile above the CPU tile, which you claim serves an I/O purpose, is only 9.0 mm x 1.9 mm = 17.1 mm². That's in the ballpark of Thunderbolt 4 redriver chips that are designed to be embedded into cable connectors. I/O and analog tends to demonstrate worse area scaling than logic or SRAM, so what node do you think that little tile is on? In what universe would it not have been more cost effective to integrate that block into one of the other tiles?
I think it's probably some combination of Thunderbolt and/or PCIe controllers + PHY. Maybe the IPU and PHY or something else imaging related.

As for why they'd put it on there, probably shoreline. Must be cramped in the main SOC die, and I'd hate to imagine what it would be like routing high speed IO under one of the active dies. Also, it could let them support different configs for different markets. P needs more PCIe, Thunderbolt, whatever? Well then just swap out that one die instead of the whole SOC.

As for the process, I'm thinking N6 or something similar. Curious whether they use internal or external for that.
 
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dullard

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mikk

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So, I am not expecting 25-30% with a new architecture now. I think we'll see Ticks that are 7-10% faster and Tocks that are 20% faster for a total of 30% per 2 years for the P cores, and 30-something % per 2 years with the E cores.

Raptorlake: 7-10%
Meteorlake: 20%
Arrowlake: 7-10%
Lunarlake: 20%

If you add another 10% with Novalake, you get to the "Up to 2x over Golden Cove" number thrown out by MLID.


If the old reddit leak is believed Nova Lake is the biggest improvement because it's a radical change and could be the real Core successor (Royal Core). Arrow Lake and Lunar Lake using the same Cove and Mont is the big question. At the very least we can say the reddit leak wasn't just a troll posting.
 

mikk

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Looks like they changed the Meteorlake graphics architecture from DG2 based to Battlemage DG3 based. Good thing because the architecture in DG2 isn't particularly competitive.

Some say Raja will have a hard time since he was handed the "worst" GPU architecture in the industry.


Where do you see this? The graphics driver clearly lists both MTL+ARL as either Xe HPG or Gen12.7 and both is DG2 generation. DG3 is Xe2 or Gen12.9 which is coming in the Lunar Lake generation. And how you can say DG2 isn't particularly competitive when it isn't out yet and you can't know how it exactly performs and how much power it needs?
 

Exist50

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Isn't that a 56 core processor ? So if something breaks, they sell it as a 42 core or a 28 core processor ?
If my understanding is correct, it would be something like if a core breaks, they can just disable that core and otherwise be fine. Though I will say that 76% seems kind of low if that's actually the metric. There's also definitely some degree of fault tolerance in there though. I think Apple goes hardest on that.
 
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jpiniero

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If my understanding is correct, it would be something like if a core breaks, they can just disable that core and otherwise be fine.

I think it's more to help the odds that a defect doesn't cause a core to need to be disabled or even the whole chip if it's something that would cause it to be completely busted.