Discussion Intel current and future Lakes & Rapids thread

[Cardyak]

In the realm of crazyness. Got this dropped...

Project << Starwars Moon? >>
ISA << IA-FUTURE >>
Node << Intel 5nm >>

From the later cove core to the above is the equivalent aggregate perf/watt enhancement of P5 on 0.8 μm to the later cove core. <== Other than the vague info.

5nm development has started.
5nm memories will be next.
5nm logic will be after.
5nm microarchitectures+other ip after that.
w/ the launch being a short time from now in a foundry very, very near....

Regardless, I'm going to distance myself even further from these "intel" people.

Almost certain I'm taking the bait here, but this is an interesting post regardless.

Okay so first of all - This sounds far to good to be true. You mean the gap in perf/watt on the latest cove compared to this new super-secret architecture is better than all of the perf/watt increases from the latest Cove to the P5? First of all can you clarify what the phrase "Later cove core" means? Are we referring to Sunny, Willow, Golden, or even something later?

Surely the designs for Intel's 5nm architectures are way to far out to really offer any granular detail on performance metrics?

 

[NostaSeronx]

Okay so first of all - This sounds far to good to be true. You mean the gap in perf/watt on the latest cove compared to this new super-secret architecture is better than all of the perf/watt increases from the latest Cove to the P5? First of all can you clarify what the phrase "Later cove core" means? Are we referring to Sunny, Willow, Golden, or even something later?

Where I found it didn't specify what Cove core it was talking about on the roadmap. Other than it was later rather than earlier, since we only know about Goldencove, I originally had Goldencove in the spot.
Palmcove (10nm) -> Sunnycove (10nm+) -> Willowcove(10nm++) -> Goldencove (10nm+++) -> --- Cove (7nm) -> --- Cove (7nm+) --> "Deadsun 1" (7nm++) -> "Deadsun 2" (5nm)

Most of it was about the first 5nm CPU core only though. DS1 will go half-way(probaby, the 7nm up-port wasn't mentioned at all) and DS2 will go all the way.

Surely the designs for Intel's 5nm architectures are way to far out to really offer any granular detail on performance metrics?

Anything canned between May 3, 2013 to June 21, 2018 might be back on the table. Also, compared to previous architectures this one has the most funding comparatively. The architecture is being worked on by all teams with C2DG/Haifa team being in command seat from the get-go. Rather, than build it at Folsom or Oregon and have Haifa fix it if it isn't feasible for production. It is particularly an all-in architecture, much like how AMD went with Zen.

I'm currently watching for any updates with;
BiTS team (known work on IA32 EL/Houdini/IA32 and Intel 64 DBT instructions)
DRVFS team (known work on SoftMachines)
EPIC team (known work on EPIC ISA and EPIC instruction set extentsion to IA32/Intel 64)

For the potential perf/watt improvements and IA-FUTURE.

The metrics are probably from planning and simulations with the 7nm risk production. With the increased margin of hitting the end goal with the 5nm node.

DBT unit shouldn't translate between ARM instruction to x86 instruction. (Specifically, the DBT unit is after the decoder not before it) Rather, converts decoded R/M/I operand/addresses from physical(ex. finite(R0-R15)) to virtual(ex. infinite(vR0-vR∞)). As well as some other features allowing for thread rotations, as well as automatic fencing. (Which is used in conjuction with the consistency/security manager around the retire/scheduler)

 

[Exist50]

Almost certain I'm taking the bait here, but this is an interesting post regardless.

Don't be fooled. That is 100% BS. Nosta's post history is almost entirely nonsensical technobabble he pulled out of the ether. It may include technical-sounding language in some places (note, merely sounding), but it has zero connection with reality.

 

[jpiniero]

I think what that note really means that they won't start producing the fixed version until they also start on Rocket-S.

Remember it's like 3+ months from when production starts.

 

[Ajay]

No. As of Q4'18 (Last time Intel updated this slide) Intel "only" had 3 14nm Fabs online, though I imagine pretty large fabs at that and since then they have expanded the capacity of those fabs.

View attachment 20300

Well, I'm finding it hard to source more recent info, but I thought, for instance, that all four D1 series fabs in Oregon were doing 14nm. One Hillsboro(D1X - though maybe only the recent expansion) fab and one in Chandler(42) are tooling up for 7nm. I haven't read anything besides that. I don't know why it's so hard to find this info - one would expect that info to get out in industry news outlets. The BIG fabs are D1X (Hillsboro), 42 (Chandler), 28 (Kiryat Gat) and 24 (Leixlip).

 

[Ajay]

If...

And the answer is pretty sure no. They can use 10nm for desktop for another couple years. I'm going to suggest that desktop is now the last class citizen. Mobile and server gets new process first, desktop lags behind. And for mobile it will also only be part of the lineup. Most will go to servers (CPU and accelerators).

You got me, 'when'...
Yeah, I suppose desktop would be last as Intel is supposed to be doing server first. Still, desktop cannot lag very far behind because 10nm just isn't going to have the required volume (barring a miracle).

 

[jpiniero]

Videocardz has an update saying that Intel is already producing the fixed version of the Foxville controller. So I don't think you can read into Rocket Lake-S's release by that earlier note.

 

[SAAA]

MSI MS-7A78 vs Intel Corporation Tiger Lake Client Platform - Geekbench

Some quad core Tiger Lake sample beating old Kaby Lake, 4.2 GHz max frequency for the beast. Let's see how Rocket plays out.

 

[DrMrLordX]

@SAAA

Looks like AES performance is skewing the score in Tiger Lake's favor in ST. In MT, it's AES and Speech recognition. Also, it looks like Kaby had a ~300 MHz clockspeed advantage. So not too bad really.

 

[IntelUser2000]

Looks like AES performance is skewing the score in Tiger Lake's favor in ST. In MT, it's AES and Speech recognition. Also, it looks like Kaby had a ~300 MHz clockspeed advantage. So not too bad really.

I almost never use the built-in comparison tool because it doesn't break it down into categories. Comparing it individually shows the Single Thread, Integer score, which is what perf/clock really is.

According to that, with 7% advantage in favor of Kabylake, Tigerlake does 3.9% better.

But I'd be wary of making comparisons based on a single result. Only final reviews with the same testing environment is the way to go. You don't know with two different testers what things they are doing differently. That's why user-submitted results such as Geekbench can vary wildly. You can see *identical* setups getting 30% better. It's pretty much you look at the result and say "Oh cool" and no more no less.

@Exist50 I do not think I'm being pessimistic by stating 4.3GHz. The cores are going to have a perf/clock advantage and it'll clock 10% higher. That's a very decent gain. Whiskeylake performs identically to Icelake in ST, which means Tigerlake will be that much faster(perf/clock + clock over ICL).

But this is likely why we have Rocketlake, as the 10nm is nowhere near mature. The cores are completely new, but the process itself is probably characterized in every which way possible.

 

[Exist50]

@Exist50 I do not think I'm being pessimistic by stating 4.3GHz. The cores are going to have a perf/clock advantage and it'll clock 10% higher. That's a very decent gain. Whiskeylake performs identically to Icelake in ST, which means Tigerlake will be that much faster(perf/clock + clock over ICL).

I suppose this would be a good time to mention the new leak claiming the i7-1185G7 will have a 4.7GHz boost clock.

https://m.weibo.cn/status/4497220525148079

I have no connection to the leaker, but they previously leaked a Comet Lake S document, so there's some measure of credibility.

https://www.tomshardware.com/uk/new...mance-up-to-30-percent-gain-in-threaded-tests

In any case, the one thing I don't expect is significant IPC gains. Oh the cache will probably buy them a bit, and maybe there'll be other small changes here and there, but none of the leaks thus far seem to suggest a significant IPC improvement.

The cores are going to have a perf/clock advantage and it'll clock 10% higher. That's a very decent gain. Whiskeylake performs identically to Icelake in ST, which means Tigerlake will be that much faster(perf/clock + clock over ICL).

Isn't that statement kind of sad? For any other company (Apple, ARM, even AMD), a 10% gain a year after a near-zero gain would be called terribly disappointing. We're used to like twice that rate in mobile.

But this is likely why we have Rocketlake, as the 10nm is nowhere near mature. The cores are completely new, but the process itself is probably characterized in every which way possible.

Rocket Lake's existence can be justified regardless of 10nm yields and performance, if for no other reason than it's dirt cheap. I expect Intel to make boatloads of profit by dumping Rocket Lake on the enterprise laptop market, and gamers will probably eat up Rocket Lake S regardless of power consumption. Though by that point AMD's likely to be essentially equal in single thread.

 

[coercitiv]

Rocket Lake's existence can be justified regardless of 10nm yields and performance, if for no other reason than it's dirt cheap. I expect Intel to make boatloads of profit by dumping Rocket Lake on the enterprise laptop market, and gamers will probably eat up Rocket Lake S regardless of power consumption.

If that were true then where was Skylake on 22nm? Where is Zen2 on 12nm? Such a theory doesn't just need to stand up to immediate scrutiny, but to historic records as well. In the best case scenario, which is little or no competition, you do what Intel did: jump on the next node but keep transistor count relatively constant. This way you control costs with great efficiency while keeping your R&D going. You almost get to keep the cake too.

Meeting demand and/or damage control are more likely candidates than cost optimization.

 

[Exist50]

If that were true then where was Skylake on 22nm? Where is Zen2 on 12nm? Such a theory doesn't just need to stand up to immediate scrutiny, but to historic records as well. In the best case scenario, which is little or no competition, you do what Intel did: jump on the next node but keep transistor count relatively constant. This way you control costs with great efficiency while keeping your R&D going. You almost get to keep the cake too.

Meeting demand and/or damage control are more likely candidates than cost optimization.

Well they clearly developed Rocket Lake in the first place as a backup plan for continued 10nm failures, but with that work mostly done, they might as well use it.

 

[mikk]

I suppose this would be a good time to mention the new leak claiming the i7-1185G7 will have a 4.7GHz boost clock.

https://m.weibo.cn/status/4497220525148079

If true my bet for the i7-1165G7 Turbo is 4.5 Ghz. That was my initial expection a few months ago and based on the early ES I think this is realistic. In general Intel is extremely defensive about Tigerlake, they haven't even published their GDC Xe primer which was scheduled for April.

 

[uzzi38]

In general Intel is extremely defensive about Tigerlake, they haven't even published their GDC Xe primer which was scheduled for April.

Expect something soon-ish. Probably in the next month

 

[Ajay]

If true my bet for the i7-1165G7 Turbo is 4.5 Ghz. That was my initial expection a few months ago and based on the early ES I think this is realistic. In general Intel is extremely defensive about Tigerlake, they haven't even published their GDC Xe primer which was scheduled for April.

Expect something soon-ish. Probably in the next month

Good lord I hope we get some solid info soon. The rumors are just killing me. There is such a fog over everything 10nm.

 

[lobz]

MSI MS-7A78 vs Intel Corporation Tiger Lake Client Platform - Geekbench

Some quad core Tiger Lake sample beating old Kaby Lake, 4.2 GHz max frequency for the beast. Let's see how Rocket plays out.

Rocket Lake has nothing to do with Tiger Lake on the CPU side.

 

[DrMrLordX]

Rocket Lake has nothing to do with Tiger Lake on the CPU side.

Isn't it also Willow Cove?

 

[kostarum]

Rocket Lake has nothing to do with Tiger Lake on the CPU side.

excuse me??? where you get that?

Gesendet von meinem JSN-AL00 mit Tapatalk

 

[lobz]

Isn't it also Willow Cove?

What a strange forum this is. Half the people swear it's not a backport, and the other half pretends it's a given.
I really can't see that big of a core being thermally feasible on 14nm, let alone as an 'S' product.

 

[maddie]

excuse me??? where you get that?

Gesendet von meinem JSN-AL00 mit Tapatalk

WOW. 3 posts in 11 yrs.

 

[coercitiv]

WOW. 3 posts in 11 yrs.

don't underestimate exponential growth

 

[DrMrLordX]

What a strange forum this is. Half the people swear it's not a backport, and the other half pretends it's a given.
I really can't see that big of a core being thermally feasible on 14nm, let alone as an 'S' product.

If it isn't a backport, then what is it?

 

[SAAA]

What a strange forum this is. Half the people swear it's not a backport, and the other half pretends it's a given.
I really can't see that big of a core being thermally feasible on 14nm, let alone as an 'S' product.

The thermally feasible sounds completely silly to me, like it's surely more feasible than in a denser node temperatures wise: you only get better by spreading components apart. We are long past the point were a smaller node has twice the power efficiency and can be as cool if not lower temp than the previous one, that scaling is truly dead.
Now clocks will be another matter but there I expect the IPC advantage to take back any single thread loss and some more.

OK, maybe it won't be full Willow cores with AVX512 and larger caches but definitely something new, else how do you recoup the 2 less core? Why release 8 core max after 10 core Comet Sky Lake?

If there were rumors of 12 core Rocket Lake I would have no troubles believe it's the same exact arch again, but this time they designed motherboards with PCIe 4.0 in mind and the chip is rumored to have gen12 GPU: there's a 90% chance it's Willow Cove backport, with the 10% being Sunny Cove in my opinion.

 

[coercitiv]

I think Intel had a problem with die size, not thermals.

rocketlake.SKYLAKE pun intended.