I mean, it's on the borderline of "feasible" with the 10 core CML. Either they have to use denser libraries, or.... did just Intel suddenly start to think that producing MUCH larger dice for roughly the same price, thus further reducing profit margin is OK? That really didn't seem their way of thinking so far. I'm not trying to be funny or rude here, I just think that both moves are bad.@naukkis
Intel confirmed multiple times that they'll backport cores. It's not about 14nm being better than 10nm. Allowing backports mean you can keep up with demand and provide an alternative in case the latest process fails.
@lobz It's totally "thermally feasible". 10nm has advantages in lower power and clocks but not at high frequencies. The variant in Tigerlake will do a lot to improve there but maybe still bit behind 14nm.
Hence the talk about them using chiplets. But we'll see if that actually ends up happening.I mean, it's on the borderline of "feasible" with the 10 core CML. Either they have to use denser libraries, or.... did just Intel suddenly start to think that producing MUCH larger dice for roughly the same price, thus further reducing profit margin is OK?
You don't think we will see ICL Xeons this year?At this point, nobody could convince me that ICL sales covered more than 1-2% of what 10nm """development""" cost so far. As for ICL servers? Starting to turn into a Cannon Lake gig.
And those engineers would have been wrong. Not having EUV is part of the reason that 10nm was so borked in the first place. Intel process engineers threw the kitchen sink at 10nm trying to get the density they wanted. So much for that approach. Still, Intel had to push through 10nm on the way to 7 anyway, once committed, they had to learn from their mistakes so as not to repeat them on 7nm. Sorta the same situation when TSMC put out 20nm, even though it was pretty rough and had few big design wins.I'm 1000% sure there were engineers who told the management very early on to scrap 10nm and pull forward a much less agressive 7nm (not _that_ dense and withouht EUV for the first iteration). I don't think it could have been any harder, any more time consuming and more importantly, financially much more forgiving than spending years and countless billions to fix a fundamentally broken process.
Intel swears up and down we'll see them. After all the delays, I'm not sure they'll matter much. Intel is doing a good job of selling more Cascade Lake.You don't think we will see ICL Xeons this year?
Chiplet design is great for heavy multicore applications... like servers. This is the main market I'd expect it from Intel at 1st place. Alder Lake is kind of surprasing however it can be just side effect similar to what AMD did. Low-leak efficient dies goes to server and high-leak high-clock dies and partly disabled goes to desktop. If chiplet design brings huge benefits, and it does, than soon or later Intel will adopt that too.Hence the talk about them using chiplets. But we'll see if that actually ends up happening.
No, I'm sure they will 'launch' it and it will be 'shipping for revenue' /smhYou don't think we will see ICL Xeons this year?
Definitely is destined to be like Cooper in that it only ends up shipping to a few customers at best.No, I'm sure they will 'launch' it and it will be 'shipping for revenue' /smh
They'll make one someone an offer they can't refuse. Presto, revenue of the books. Investors satisfied that Intel delivered on promise, just so long as the money train keeps rolling.No, I'm sure they will 'launch' it and it will be 'shipping for revenue' /smh
Exactly.They'll make one someone an offer they can't refuse. Presto, revenue of the books. Investors satisfied that Intel delivered on promise, just so long as the money train keeps rolling.
It would be a shame if something were to happen to your business. Capiche?They'll make one someone an offer they can't refuse.
PCIe Gen 5 isn't coming to consumers to soon, and certainly not before DDR5 support. Far too costly.Interesting information about ADL-S and the LGA1700 platform.
Looks like ADL-S will have both big+little cores as previously leaked, using the Golden Cove and Gracemont (with AVX512 support!!) cores.
The small cores are for mobile, but S is going to be along for the ride. It does allow marketing to say the top model has 16 cores.I wouldn't trust with certainty anything leaked on the Chiphell forums. It still doesn't make sense as to why one would scale up a low power design for a high power platform.
I guess it makes sense to add AVX512 to Gracemont for ISA compatibility, but I doubt it will be fast AVX512.Interesting information about ADL-S and the LGA1700 platform.
Looks like ADL-S will have both big+little cores as previously leaked, using the Golden Cove and Gracemont (with AVX512 support!!) cores.
If they go the route of using MCM for Alderlake I assume it'll only be the IMC/PCI Express/Graphics that are on the seperate chip. Richie's assumption that Gracemont and Golden Cove will be seperated are completely ridiculous, because you lose any point of doing such a configuration.Hence the talk about them using chiplets. But we'll see if that actually ends up happening.
I'm not sure what to make of that rumor. I can believe Alder Lake is big.LITTLE, but the rest just seems kinda off. By 2021-2022, one would hope DDR5 support is a given, so why is he even questioning it. PCIe 5.0 support should also be somewhat likely, if not for Alder Lake, then at least Meteor Lake timeline.Interesting information about ADL-S and the LGA1700 platform.
Looks like ADL-S will have both big+little cores as previously leaked, using the Golden Cove and Gracemont (with AVX512 support!!) cores.
I think they'll be quicker to cut the big cores than Atom cores. So something more like:The small cores are for mobile, but S is going to be along for the ride. It does allow marketing to say the top model has 16 cores.
So something like:
i9: 8+8
i7: 8+4
i5: 6+0
i3: 4+0
Tremont cores are about 1/4th the size of Sunny Cove. If Gracemont and Golden Gove maintain that ratio, then it's easy to see why an 8 core Atom die would be pointless. Would be so tiny that the overhead wouldn't justify its existence. Far better to just have a single 8+8 die.If they go the route of using MCM for Alderlake I assume it'll only be the IMC/PCI Express/Graphics that are on the seperate chip. Richie's assumption that Gracemont and Golden Cove will be seperated are completely ridiculous, because you lose any point of doing such a configuration.
The support is likely going to be similar to how AMD's Jaguar worked with AVX. So it'll take several cycles to execute one AVX-512 instruction. AVX-512 support is mandatory for the "little" cores unless they want to disable it again on Golden Cove cores like they did with Lakefield.Also, skeptical of AVX-512 on Gracemont. AVX2 I can definitely see, but if AVX-512 support exists, it would definitely have to be through microcode only.
I agree with this too. But the leak showed 8+8+1 125W, 8+8+1 80W, and 6+0+1 80W.I think they'll be quicker to cut the big cores than Atom cores. So something more like:
There's a full slide of it at Notebookcheck.Supposedly when some OEM gets supply of Tiger Lake.
In other words, this is probably when it ships to OEMs. The OEM in question seems to be a major one if they're using Lakefield (as not many are).