It must be either Willow Cove or Sunny Cove. The RAM speed and L2 cache size suggests Sunny Cove, even though there is no confirmed information.Isn't it also Willow Cove?
It must be either Willow Cove or Sunny Cove. The RAM speed and L2 cache size suggests Sunny Cove, even though there is no confirmed information.Isn't it also Willow Cove?
First design of new node is basically little bit modified previous node design. For 10nm it was Cannonlake. And as seen there's no path from later designs to previous node. Willow Cove is already ++ design.
Where? It's different thing to use their newer IP to 14nm designs than backporting whole core.Intel confirmed multiple times that they'll backport cores.
Next year there is RKL-S. ADL-S is something for 2022 (or very late 2021 but I doubt). Also ADL-S is probably based on 10++ while Tigerlake-U is 10+ based, further improvements are a given. Furthermore, based on the latest leak ADL-S only comes with 8 big cores together with 8 small cores, it's rather small for 10nm.Regarding Alder Lake> Intel has currently yields problems with 4-core Ice Lake at 10nm and next year they will produce 16-core monolith Alder Lake? That's very strange jump.
It's 8 Golden Cove cores and 8 Gracemont cores. We don't know how large either are, but even an 8 core TGL-H die - depending on how much gets cut down from the TGL-U variant like the IPU etc - would probably sit around 180mm^2 - 200mm^2. Golden Cove will almost no doubt be even larger than that, so I wouldn't be surprised to see a die around the size as Comet Lake-S's 198mm^2 die.Next year there is RKL-S. ADL-S is something for 2022 (or very late 2021 but I doubt). Also ADL-S is probably based on 10++ while Tigerlake-U is 10+ based, further improvements are a given. Furthermore, based on the latest leak ADL-S only comes with 8 big cores together with 8 small cores, it's rather small for 10nm.
Nobody here uses the term "backport" as loading the 10nm design on a floppy disk and printing on the old 14nm dot matrix machine.Where? It's different thing to use their newer IP to 14nm designs than backporting whole core.
Raja Koduri / Jim Keller said:Our products will be decoupled from our transistor capability. We have incredible IP at Intel, but it was all sitting in the 10nm process node. If we had had it on 14nm then we would have better performance on 14nm. We have a new method inside the company to decouple IP from the process technology. You must remember that customers buy the product, not a transistor family. It’s the same transformation AMD had to go through to change the design methodology when they were struggling. At Apple it was called the ‘bus’ method.
The article I linked in my previous post was also about this: Intel makes sure they have "good abstractions in product and process node going forward", hence they can lock in the node for a specific product much later in the development process. They still have to commit, but not the way they did until Cannon Lake / Ice Lake.Dr. Murthy Renduchintala said:We now have to make sure that our IP is not node-locked. The ability to have portability of IP across multiple nodes is great for contingency planning. We will continue to take aggressive risks in our designs, but we also will have contingency. We need to have as much of a seamless roadmap as possible in case those contingencies are needed, and need to make sure they are executed on ASAP if needed to keep the customer expectations in line. You will see future node technologies, such as 10/7, have much more overlap than before to keep the designs fluid. Our product portfolio on 14nm could have been much better if our product designs were not node-locked to 10nm.
Exactly. Sunny Cove core in Ice Lake was +30% in transitors over Coffee Lake so Golden Cove could be very easy around 40% increase. Tiger Lake is 146mm2 so 8-cores is around 190mm2 and Golden Coves would be around 220mm2. Plus 8-cores of Gracemont it can be 250mm2. For servers why not. But it's just too big for desktop IMHO.It's 8 Golden Cove cores and 8 Gracemont cores. We don't know how large either are, but even an 8 core TGL-H die - depending on how much gets cut down from the TGL-U variant like the IPU etc - would probably sit around 180mm^2 - 200mm^2. Golden Cove will almost no doubt be even larger than that, so I wouldn't be surprised to see a die around the size as Comet Lake-S's 198mm^2 die.
This is a flawed estimate because Tigerlake-U features a GT2 iGPU with 96 EUs while TGL-H and ADL-S only gets a GT1 iGPU with 32 EUs, this could save 20-30mm². Furthermore some parts of a chip won't linearly increase with the amount of cores, for example the memory controller or uncore. TGL-H might be slightly bigger than TGL-U but surely not 30%, your estimate is flawed.Exactly. Sunny Cove core in Ice Lake was +30% in transitors over Coffee Lake so Golden Cove could be very easy around 40% increase. Tiger Lake is 146mm2 so 8-cores is around 190mm2 and Golden Coves would be around 220mm2. Plus 8-cores of Gracemont it can be 250mm2. For servers why not. But it's just too big for desktop IMHO.
When you say my estimation is flawed please provide yours Alder Lake monolith estimation. Ice Lake has 122mm2 so it's 24mm2 difference from 146mm2 TGL for CPU uarch, GPU and L2 (+150%) & L3 (+50%) cache increases. So it cannot be more than 24mm2 just for GPU as you suggests. GT1 GPU itself could save around 15mm2?This is a flawed estimate because Tigerlake-U features a GT2 iGPU with 96 EUs while TGL-H and ADL-S only gets a GT1 iGPU with 32 EUs, this could save 20-30mm². Furthermore some parts of a chip won't linearly increase with the amount of cores, for example the memory controller or uncore. TGL-H might be slightly bigger than TGL-U but surely not 30%, your estimate is flawed.
Well rejoice, I actually tried estimating with what I have and I got between 150-175mm^2, depending on if the IPU and TB4 are cut out (subtract roughly 7mm^2 for the first and 14mm^2 for the second, plus some blank space which I didn't know what to do with made up the rest).This is a flawed estimate because Tigerlake-U features a GT2 iGPU with 96 EUs while TGL-H and ADL-S only gets a GT1 iGPU with 32 EUs, this could save 20-30mm². Furthermore some parts of a chip won't linearly increase with the amount of cores, for example the memory controller or uncore. TGL-H might be slightly bigger than TGL-U but surely not 30%, your estimate is flawed.
There is no data for ADL-S available apart from the core count and therefore no serious estimate is possible. Even your +40% bigger statement is bold, it's a random guess at the moment. You definitely should use the core size and not the size from the entire chip. Your estimate based on the entire Icelake-U/Tigerlake-U chip is definitely flawed, you didn't take into account the graphics.When you say my estimation is flawed please provide yours Alder Lake monolith estimation.
Icelake-U GT2= 64 EUs Gen11Ice Lake has 122mm2 so it's 24mm2 difference from 146mm2 TGL for CPU uarch, GPU and L2 (+150%) & L3 (+50%) cache increases. So it cannot be more than 24mm2 just for GPU as you suggests. GT1 GPU itself could save around 15mm2?
Are you serious? Somebody pretty seriously insist that RocketLake cores are same Willow Cove as used in Tigerlake, which means just that above.Nobody here uses the term "backport" as loading the 10nm design on a floppy disk and printing on the old 14nm dot matrix machine.
Yes, Rocketlake will have new 14nm based cpu cores, which will be new core build for 14nm, and probably more closely related to Skylake than Willow Cove.Everybody talks about using the IP to build a 14nm equivalent core. Intel themselves made this abundantly clear since 2 years ago.
This statement is strange because Willow Cove is a refresh of Sunny Cove, beside the cache redesign there isn't much new as far as we know. It's like saying Sunny Cove is more closely related to Skylake than Willow Cove which is nonsense.probably more closely related to Skylake than Willow Cove.
You would think it would be easier from a validation perspective to basically backport Willow Cove back than to try to make some bastard version if it. Now it doesn't have Willow Cove's additional cache but it does have AVX-512.Are you serious? Somebody pretty seriously insist that RocketLake cores are same Willow Cove as used in Tigerlake, which means just that above.
Exactly! Now sure why people are making such a big deal between Sunny Cove and Willow Cove as the differences between them are small and the performance increase they both provide over Skylake cores will be very large.This statement is strange because Willow Cove is a refresh of Sunny Cove, beside the cache redesign there isn't much new as far as we know. It's like saying Sunny Cove is more closely related to Skylake than Willow Cove which is nonsense.
And Intel has said that backporting Sunny Cove to 14nm is impossible.This statement is strange because Willow Cove is a refresh of Sunny Cove, beside the cache redesign there isn't much new as far as we know. It's like saying Sunny Cove is more closely related to Skylake than Willow Cove which is nonsense.
Intel never said that.And Intel has said that backporting Sunny Cove to 14nm is impossible.
What is your source and how old is it? I haven't heard anything like this in the past 18 months, Intel is very secretive lately. Actually Intel hinted at the architecture day in December 2018 that only the first Sunny Cove products will be on 10nm, so if RKL gets Sunny Cove cores this interview become reality.And Intel has said that backporting Sunny Cove to 14nm is impossible.
I mean, it's on the borderline of "feasible" with the 10 core CML. Either they have to use denser libraries, or.... did just Intel suddenly start to think that producing MUCH larger dice for roughly the same price, thus further reducing profit margin is OK? That really didn't seem their way of thinking so far. I'm not trying to be funny or rude here, I just think that both moves are bad.@naukkis
Intel confirmed multiple times that they'll backport cores. It's not about 14nm being better than 10nm. Allowing backports mean you can keep up with demand and provide an alternative in case the latest process fails.
@lobz It's totally "thermally feasible". 10nm has advantages in lower power and clocks but not at high frequencies. The variant in Tigerlake will do a lot to improve there but maybe still bit behind 14nm.