Discussion Intel current and future Lakes & Rapids thread

[mikk]

Isn't it also Willow Cove?

It must be either Willow Cove or Sunny Cove. The RAM speed and L2 cache size suggests Sunny Cove, even though there is no confirmed information.

 

[naukkis]

They kinda' did.

View attachment 20416

First design of new node is basically little bit modified previous node design. For 10nm it was Cannonlake. And as seen there's no path from later designs to previous node. Willow Cove is already ++ design.

 

[IntelUser2000]

@naukkis

Intel confirmed multiple times that they'll backport cores. It's not about 14nm being better than 10nm. Allowing backports mean you can keep up with demand and provide an alternative in case the latest process fails.

@lobz It's totally "thermally feasible". 10nm has advantages in lower power and clocks but not at high frequencies. The variant in Tigerlake will do a lot to improve there but maybe still bit behind 14nm.

 

[Richie Rich]

Regarding Alder Lake> Intel has currently yields problems with 4-core Ice Lake at 10nm and next year they will produce 16-core monolith Alder Lake? That's very strange jump. It's improbable in terms of yields. IMHO Intel adopted AMD's chiplet design for Alder Lake using separate chiplet for 8-core Golden Cove part and another for 8-core Gracemont part. There are few point supporting this:

• chiplet design has some very nice benefits as seen in AMD's Zen2 so it's just matter of time when Intel adopts/copy that too
• timing could be 2 years after Zen2 reveal in 2019.... so it's exactly Alder Lake range (assuming IP changes could take about 2 years)
• leak suggested some strange configurations for monolith: 8+8 is difficult in yields, 6+0 is economy nonsence disabling all small cores (there is much higher defect probability in larger Golden Cove cores) so it pragmatic to not use small cores chiplet at all (and use it in server Snow Ridge instead).

Of course Intel can use it's own chiplet tech like EMIB or Foveros interposer. But it looks to me Intel

 

[naukkis]

Intel confirmed multiple times that they'll backport cores.

Where? It's different thing to use their newer IP to 14nm designs than backporting whole core.

 

[mikk]

Regarding Alder Lake> Intel has currently yields problems with 4-core Ice Lake at 10nm and next year they will produce 16-core monolith Alder Lake? That's very strange jump.

Next year there is RKL-S. ADL-S is something for 2022 (or very late 2021 but I doubt). Also ADL-S is probably based on 10++ while Tigerlake-U is 10+ based, further improvements are a given. Furthermore, based on the latest leak ADL-S only comes with 8 big cores together with 8 small cores, it's rather small for 10nm.

 

[uzzi38]

Next year there is RKL-S. ADL-S is something for 2022 (or very late 2021 but I doubt). Also ADL-S is probably based on 10++ while Tigerlake-U is 10+ based, further improvements are a given. Furthermore, based on the latest leak ADL-S only comes with 8 big cores together with 8 small cores, it's rather small for 10nm.

It's 8 Golden Cove cores and 8 Gracemont cores. We don't know how large either are, but even an 8 core TGL-H die - depending on how much gets cut down from the TGL-U variant like the IPU etc - would probably sit around 180mm^2 - 200mm^2. Golden Cove will almost no doubt be even larger than that, so I wouldn't be surprised to see a die around the size as Comet Lake-S's 198mm^2 die.

 

[coercitiv]

Where? It's different thing to use their newer IP to 14nm designs than backporting whole core.

Nobody here uses the term "backport" as loading the 10nm design on a floppy disk and printing on the old 14nm dot matrix machine.

Everybody talks about using the IP to build a 14nm equivalent core. Intel themselves made this abundantly clear since 2 years ago.

Our products will be decoupled from our transistor capability. We have incredible IP at Intel, but it was all sitting in the 10nm process node. If we had had it on 14nm then we would have better performance on 14nm. We have a new method inside the company to decouple IP from the process technology. You must remember that customers buy the product, not a transistor family. It’s the same transformation AMD had to go through to change the design methodology when they were struggling. At Apple it was called the ‘bus’ method.

We now have to make sure that our IP is not node-locked. The ability to have portability of IP across multiple nodes is great for contingency planning. We will continue to take aggressive risks in our designs, but we also will have contingency. We need to have as much of a seamless roadmap as possible in case those contingencies are needed, and need to make sure they are executed on ASAP if needed to keep the customer expectations in line. You will see future node technologies, such as 10/7, have much more overlap than before to keep the designs fluid. Our product portfolio on 14nm could have been much better if our product designs were not node-locked to 10nm.

The article I linked in my previous post was also about this: Intel makes sure they have "good abstractions in product and process node going forward", hence they can lock in the node for a specific product much later in the development process. They still have to commit, but not the way they did until Cannon Lake / Ice Lake.

 

[IntelUser2000]

@naukkis You've been sleeping. Just like coercitive says its been known since couple of years ago.

@Richie Rich You are making zero sense. MCM on a heterogenous integration? Maybe you don't know much about the thing you are talking about than you think you do.

 

[Richie Rich]

It's 8 Golden Cove cores and 8 Gracemont cores. We don't know how large either are, but even an 8 core TGL-H die - depending on how much gets cut down from the TGL-U variant like the IPU etc - would probably sit around 180mm^2 - 200mm^2. Golden Cove will almost no doubt be even larger than that, so I wouldn't be surprised to see a die around the size as Comet Lake-S's 198mm^2 die.

Exactly. Sunny Cove core in Ice Lake was +30% in transitors over Coffee Lake so Golden Cove could be very easy around 40% increase. Tiger Lake is 146mm2 so 8-cores is around 190mm2 and Golden Coves would be around 220mm2. Plus 8-cores of Gracemont it can be 250mm2. For servers why not. But it's just too big for desktop IMHO.

What holds Intel from copying AMD's chiplet design? IMHO nothing. They need 2 years to do that and that's 2021/22 ....Alder Lake's time range. And ALD die size is on edge, strange 8+8 and 6+0 configs, and Snow Ridge server CPU based on Gracemont... all this show common intersection ... separate chiplets for 8-core Golden Cove cores and for 8-core Atom cores.

Just imagine all those possibilities Intel would have in servers based on those two chiplets. With one single 8-channel IOD he can hook up big core chiplets for standard Xeons or small core chiplet for new Snow Ridge. And as a side effect Intel can create Alder Lake combining those chiplets together to make first heterogenous desktop CPU. No wonder that no big customers wants to swap to AMD EPYCs if Intel shows them what's coming soon. Golden Cove at 10nm using chiplet design can equal the game again.

 

[mikk]

Exactly. Sunny Cove core in Ice Lake was +30% in transitors over Coffee Lake so Golden Cove could be very easy around 40% increase. Tiger Lake is 146mm2 so 8-cores is around 190mm2 and Golden Coves would be around 220mm2. Plus 8-cores of Gracemont it can be 250mm2. For servers why not. But it's just too big for desktop IMHO.

This is a flawed estimate because Tigerlake-U features a GT2 iGPU with 96 EUs while TGL-H and ADL-S only gets a GT1 iGPU with 32 EUs, this could save 20-30mm². Furthermore some parts of a chip won't linearly increase with the amount of cores, for example the memory controller or uncore. TGL-H might be slightly bigger than TGL-U but surely not 30%, your estimate is flawed.

 

[Richie Rich]

This is a flawed estimate because Tigerlake-U features a GT2 iGPU with 96 EUs while TGL-H and ADL-S only gets a GT1 iGPU with 32 EUs, this could save 20-30mm². Furthermore some parts of a chip won't linearly increase with the amount of cores, for example the memory controller or uncore. TGL-H might be slightly bigger than TGL-U but surely not 30%, your estimate is flawed.

When you say my estimation is flawed please provide yours Alder Lake monolith estimation. Ice Lake has 122mm2 so it's 24mm2 difference from 146mm2 TGL for CPU uarch, GPU and L2 (+150%) & L3 (+50%) cache increases. So it cannot be more than 24mm2 just for GPU as you suggests. GT1 GPU itself could save around 15mm2?

 

[uzzi38]

This is a flawed estimate because Tigerlake-U features a GT2 iGPU with 96 EUs while TGL-H and ADL-S only gets a GT1 iGPU with 32 EUs, this could save 20-30mm². Furthermore some parts of a chip won't linearly increase with the amount of cores, for example the memory controller or uncore. TGL-H might be slightly bigger than TGL-U but surely not 30%, your estimate is flawed.

Well rejoice, I actually tried estimating with what I have and I got between 150-175mm^2, depending on if the IPU and TB4 are cut out (subtract roughly 7mm^2 for the first and 14mm^2 for the second, plus some blank space which I didn't know what to do with made up the rest).

...theeeeen I realised I forgot to scale up PCIe lanes. After some asking around (thanks @OriAr). The extra 20 PCIe (CPU+direct NVMe according to Sharkbay) lanes adds on roughly an extra 22mm^2 to both of those, leaving us at a final estimation of roughly 172mm^2 - 195mm^2.

So uh, I was right, but for the wrong reasons I guess?

 

[mikk]

When you say my estimation is flawed please provide yours Alder Lake monolith estimation.

There is no data for ADL-S available apart from the core count and therefore no serious estimate is possible. Even your +40% bigger statement is bold, it's a random guess at the moment. You definitely should use the core size and not the size from the entire chip. Your estimate based on the entire Icelake-U/Tigerlake-U chip is definitely flawed, you didn't take into account the graphics.

Ice Lake has 122mm2 so it's 24mm2 difference from 146mm2 TGL for CPU uarch, GPU and L2 (+150%) & L3 (+50%) cache increases. So it cannot be more than 24mm2 just for GPU as you suggests. GT1 GPU itself could save around 15mm2?

Icelake-U GT2= 64 EUs Gen11
Tigerlake-U GT2= 96 EUs Gen12
Tigerlake-H/ADL-S GT1= 32 EUs Gen12

Gen12 graphics is much more area efficient than Gen11, I'm talking about 32 EUs Gen12 vs 96 EUs Gen12. 32 EUs Gen12 are much smaller than 64 EUs Gen11. And who knows if 10nm density is identical to 10+/10++?

 

[uzzi38]

Do the forums have a block button or something? He's purposefully blanking me for some reason, hell if I know what.

Someone tell him the 4 core CPU cluster of Tiger Lake is larger than the 96EUs by at least 20% or so will ya? I didn't measure it, but yeah, it's definitely larger.

Also, you need to account for scaled up PCIe lane count from 4 off the CPU to 20, so that adda an extra ~20mm'2 (I measured 22mm^2, but not like the thing I've got is precise enough for me to estimate better).

All in all, yes, 172-195mm^2 is a perfectly reasonable expectation.

 

[naukkis]

Nobody here uses the term "backport" as loading the 10nm design on a floppy disk and printing on the old 14nm dot matrix machine.

Are you serious? Somebody pretty seriously insist that RocketLake cores are same Willow Cove as used in Tigerlake, which means just that above.

Everybody talks about using the IP to build a 14nm equivalent core. Intel themselves made this abundantly clear since 2 years ago.

Yes, Rocketlake will have new 14nm based cpu cores, which will be new core build for 14nm, and probably more closely related to Skylake than Willow Cove.

 

[vstar]

Linux support for RKL:

[Intel-gfx] [PATCH 00/23] Introduce Rocket Lake

[Intel-gfx] [PATCH 05/23] drm/i915/rkl: Add PCH support

"Rocket Lake (RKL) is another gen12 platform, so the driver support is
mostly a straightforward evolution of our existing Tiger Lake support.

One area of this patch series that's a bit non-intuitive and warrants
some extra explanation is the output handling. All four of RKL's output
ports use combo PHYs, but the hardware guys have recycled the naming
scheme from Tiger Lake. The DDI's are still named "A, B, TC1, and TC2"
even though none of them are actually connected to Type-C PHYs on this
platform. "

"Rocket Lake can pair with either TGP or CMP."

"The RKL platform has different memory characteristics from past
platforms. "

 

[mikk]

probably more closely related to Skylake than Willow Cove.

This statement is strange because Willow Cove is a refresh of Sunny Cove, beside the cache redesign there isn't much new as far as we know. It's like saying Sunny Cove is more closely related to Skylake than Willow Cove which is nonsense.

 

[jpiniero]

Are you serious? Somebody pretty seriously insist that RocketLake cores are same Willow Cove as used in Tigerlake, which means just that above.

You would think it would be easier from a validation perspective to basically backport Willow Cove back than to try to make some bastard version if it. Now it doesn't have Willow Cove's additional cache but it does have AVX-512.

It's esp important because of the security flaw fixes that the Coves have.

 

[Edrick]

This statement is strange because Willow Cove is a refresh of Sunny Cove, beside the cache redesign there isn't much new as far as we know. It's like saying Sunny Cove is more closely related to Skylake than Willow Cove which is nonsense.

Exactly! Now sure why people are making such a big deal between Sunny Cove and Willow Cove as the differences between them are small and the performance increase they both provide over Skylake cores will be very large.

 

[naukkis]

This statement is strange because Willow Cove is a refresh of Sunny Cove, beside the cache redesign there isn't much new as far as we know. It's like saying Sunny Cove is more closely related to Skylake than Willow Cove which is nonsense.

And Intel has said that backporting Sunny Cove to 14nm is impossible.

Cpu designers will simulate best performing core configurations for given manufacturing node. If Intel wasn't far off Rocket Lake will be much more similar to Skylake than to Sunny/Willow Cove which are designed for 10nm process densities. Those are huge - many structures are twice the size of Skylake(and equals manufacturing node density increase) and if directly ported to 14nm will result clock rates about half of Skylake where wire speed is limiting factor. To get better performing core than Skylake they have to adapt only parts of their new IP portfolio that can be implemented in 14nm without bloating critical area too much.

But as Intel have executed lately it's also possible that they are delivering 3GHz 300W consuming Willow Cove port on 14nm.......

 

[jpiniero]

And Intel has said that backporting Sunny Cove to 14nm is impossible.

Intel never said that.

I will say that I am not 100% convinced that it is Sunny/Willow, but the only other option really is basically just Skylake with minimal changes other than AVX-512 enabled. Which you would think marketing would step in and insist on keeping it at 10 cores even if there were groups within Intel that wanted to reduce the core count to conserve 14 nm capacity. Marketing would have a fit if the design of the top Rocket Lake-S was slower in MT than the 10900K.

 

[mikk]

And Intel has said that backporting Sunny Cove to 14nm is impossible.

What is your source and how old is it? I haven't heard anything like this in the past 18 months, Intel is very secretive lately. Actually Intel hinted at the architecture day in December 2018 that only the first Sunny Cove products will be on 10nm, so if RKL gets Sunny Cove cores this interview become reality.

2:10: "With Sunny Cove the first products will be on 10nm"
8:30: "Remember that the first products with Sunny Cove will be on 10nm, so you get the advantage of the shrink factor by moving to the new process technology"https://forums.anandtech.com/threads/anandtech-intels-architecture-day-2018.2558618/page-10#post-39686466

If it isn't Sunny Cove it must be Willow Cove. Thero is zero indication of a mainstream architecture with AVX512 support other than Sunny/Willow.

 

[DrMrLordX]

@mikk

There was Cannonlake, but I seriously doubt they'd release 14nm Cannonlake and rename it Rocket Lake.

 

[lobz]

@naukkis

Intel confirmed multiple times that they'll backport cores. It's not about 14nm being better than 10nm. Allowing backports mean you can keep up with demand and provide an alternative in case the latest process fails.

@lobz It's totally "thermally feasible". 10nm has advantages in lower power and clocks but not at high frequencies. The variant in Tigerlake will do a lot to improve there but maybe still bit behind 14nm.

I mean, it's on the borderline of "feasible" with the 10 core CML. Either they have to use denser libraries, or.... did just Intel suddenly start to think that producing MUCH larger dice for roughly the same price, thus further reducing profit margin is OK? That really didn't seem their way of thinking so far. I'm not trying to be funny or rude here, I just think that both moves are bad.

I'm 1000% sure there were engineers who told the management very early on to scrap 10nm and pull forward a much less agressive 7nm (not _that_ dense and withouht EUV for the first iteration). I don't think it could have been any harder, any more time consuming and more importantly, financially much more forgiving than spending years and countless billions to fix a fundamentally broken process.

At this point, nobody could convince me that ICL sales covered more than 1-2% of what 10nm """development""" cost so far. As for ICL servers? Starting to turn into a Cannon Lake gig.