Discussion Intel current and future Lakes & Rapids thread

[gdansk]

super not allowed (a whole lot of cloud vendors are locked into it).

Sorry, off-topic anyway I replied in the Zen 5 thread.

 

[A///]

does anyone know the veracity of pat's claim that arrow is in fab. it's almost deceitful if he were stretching the words because of how many individual nodes the ip the processor uses unless i am mixing up my processor families.

 

[lightisgood]

I got a great impression of 2Q23 earnings.
It seems that this prediction was correct.

VLSI Japan: It’s Better on the Backside

Intel announces its PowerVia technology, and scaling the backside is the next big thing. This could be Intel's moment.

www.fabricatedknowledge.com

> PowerVia is How Intel can beat TSMC.
>
> Intel is making this bet completely alone. TSMC’s insertion of BSPDN will likely happen as late as 2026.
> Meanwhile, Intel is hoping to ship PowerVia next year.
> Intel is betting the farm on PowerVia, and as you can see below, if they ship PowerVia in 2024, it will be two years ahead of TSMC.
>
> Intel is bold and pushing forward with BSPDN, and the leadership position couldn’t be a harder position to be in.
> They must create their own debug tools, optimize new EDA flows, and pursue the path alone. If they can execute, they will have a real competitive advantage.
> I want to talk about the technical benefits and challenges of PowerVia because it’s not trivial.

 

[Henry swagger]

https://twitter.com/x/status/1684863066377199617

Sapphire rapids already shipped million units.. customers must like the ai accelerators.. sierra forest should perform even bigger in sales

 

[gdansk]

does anyone know the veracity of pat's claim that arrow is in fab. it's almost deceitful if he were stretching the words because of how many individual nodes the ip the processor uses unless i am mixing up my processor families.

I think it must include some compute die. None of the other dies are likely to be 20A.

 

[DrMrLordX]

That is what i just mentioned. A multi node jump offers a significant boost in transistor budget (and hence performance). ARL will end up with massive L2/L3 caches & extreme boost clock optimizations in cpu logic due to all the extra transistors offered by the massive increase in transistor budget.

So is that why some leakers are already showing slides giving Arrow Lake a single-generation bump over Raptor Lake @ 250W? More wasted transistor budget? Yay?

Sapphire rapids already shipped million units..

DCG volume and revenue are down. That's nothing to celebrate.

 

[SiliconFly]

So is that why some leakers are already showing slides giving Arrow Lake a single-generation bump over Raptor Lake @ 250W? More wasted transistor budget? Yay?

Only yesterday, Pat said (and we knew) that they have an actual ARL silicon running in their fab. We still know nothing abt ARL performance actually. So basically, any performance projections mentioned by leakers are mere speculation at this point. Better to wait for benchmark leaks of ARL ES for a much better idea. Mostly next quarter.

 

[coercitiv]

So basically, any performance projections mentioned by leakers are mere speculation at this point. Better to wait for benchmark leaks of ARL ES for a much better idea.

Performance projections mentioned by leakers are now based on the leaked Intel internal slides. Whether you agree/believe those slides is one thing, but as far as leaks go in this industry, we are now past the point of "mere speculation" for Arrow Lake.

 

[DrMrLordX]

Mostly next quarter.

You expect Arrow Lake-S benchmarks next quarter? Legit ones provided by Intel? No, we'll just get more leaks.

 

[SiliconFly]

You expect Arrow Lake-S benchmarks next quarter? Legit ones provided by Intel? No, we'll just get more leaks.

I didn't said that

 

[DrMrLordX]

I didn't said that

Okay

You expect ANY leaked benchmarks? I still don't, at least nothing meaningful. Arrow Lake-S is over a year from launch. Any leaked benches we get now will be no more or less informative than the leaked Intel slides.

 

[SiliconFly]

Okay

You expect ANY leaked benchmarks? I still don't, at least nothing meaningful. Arrow Lake-S is over a year from launch. Any leaked benches we get now will be no more or less informative than the leaked Intel slides.

Thats what i too meant. Might not be very meaningful, but will definitely shed more light than these so called leakers!

 

[A///]

don't mind him, he huffs and puffs from time to time.

 

[clemsyn]

Intel 3 seems healthy

Intel: 3nm Node Meets Yield and Performance Targets

Intel's 3nm Granite Rapids and Sierra Forest processors on track for 2024.

www.tomshardware.com

Interesting times... Hope they get this giant ship in the right direction and give AMD some serious competition (and give us consumers great prices).

 

[H433x0n]

This drives me absolutely crazy when the media does this:

Intel 3 (previously known as 5nm) is the company's 2nd-gen process technology - Tom's Hardware

I wonder how long they'll keep that up?

 

[Ajay]

My bad. I think i didn't explain myself clearly.

(I was just comparing Zen 4 -> Zen 5 vs RPL -> ARL. Thats all)

What I was trying to say was, AMD is going from Zen 4 to Zen 5 (say N4 to N4P), and the density increase is non-existent. So, the transistor budget remains the same. The only way to increase IPC is to re-architect with the same amount of transistors (assuming the die size remains the same).

And Intel is going from RPL to ARL (say Intel 7 to 20A), the density increase is from 100 MTr/mm2 to around 300+ MTr/mm2. ARL gets 3X the transistors for the same die area.

Intel can shrink the ARL die to save cost, but I don't think they'll do that. I think the ARL die is gonna get a significantly higher transistor budget compared to RPL, And those excess transistors can easily be used to increase L2/L3 caches in the cpu tile or even increase core logic for more performance.

Just keep in mind that these MTr/mm2 numbers are from the marketing department. They represent the absolute maximum number of xtors per area from some theoretical logic/sram block (and they are probably rounded up). Real designs don't usually come close to those numbers for a whole host of numbers. It's much more helpful when companies release the actual number of xtors in a given chip (even though that includes redundancies).

 

[Hulk]

Oh my god! Zen 5 has no 3nm!?! Thats very sad. I'm gonna hope that ain't true.

Hope people remember that Raptor Lake beat the hell out of Zen 4 during launch. And it took Zen 4 3D VCache variants for AMD to reclaim the gaming performance crown. The sad fact is, Zen 4 is a TSMC N4 (5nm+) product & Raptor Lake is a Intel 7 (10nm+) product. In simple words, Zen 4 had two full-node advantage & still lagged behind Raptor Lake in many aspects.

Intel P-cores are fat but very performant. Now, if Zen 5 is gonna be stuck in the same old TSMC N4 & ARL is gonna be on 20A, it'll be a total disaster for AMD. I'm hoping Zen 5 has a 3nm variant to level the playing field. If AMD gets crushed so soon, it's not going to be good for any of us.

Remember, only after Lisa Su happened, the idiots at Intel fired all the paper pushing morons & idiotic bean-counter CEOs & brought in Pat, a true engineer. And only after he came, we now have 5 nodes in 4 years, dis-aggregation, BPD, GAA, 20A/18A, a new uArch very soon, etc. None of this would have happened if not for Lisa Su. Lets pray AMD doesn't get crushed too fast too soon.

Competition is mandatory. And IMHO:

For good Intel products, a successful AMD is mandatory.

What are the 5 nodes in 4 years?

 

[clemsyn]

What are the 5 nodes in 4 years?

Intel 7 - Intel 4 - Intel 3 - Intel 20a and Intel 18a.

Intel 7 was originally 10nm so I assume Intel 4 is 7nm, Intel3 is 5nm..

 

[H433x0n]

Intel 7 - Intel 4 - Intel 3 - Intel 20a and Intel 18a.

Intel 7 was originally 10nm so I assume Intel 4 is 7nm, Intel3 is 5nm..

It’s not going by the old metrics:

Intel 4 - 7nm
Intel 3 - 7nm+
Intel 20A - 5nm
Intel 18A - 5nm+

This would’ve been complete marketing malpractice and really misleading if they kept that old naming scheme. You can thank Samsung for this since they were the first ones to operate in bad faith.

When Intel’s 14nm first released, Morris Chang of TSMC insisted they name their competing FinFet node 16nm since by his own admission they were behind. Then Samsung swooped in to take the marketing win by naming their competitor 14nm despite it performing worse than Intel’s & TSMC’s nodes. Thus the arm’s race of node naming schemes began.

 

[SiliconFly]

don't mind him, he huffs and puffs from time to time.

I'm gonna completely agree with that!

 

[SiliconFly]

It’s not going by the old metrics:

Intel 4 - 7nm
Intel 3 - 7nm+
Intel 20A - 5nm
Intel 18A - 5nm+

This would’ve been complete marketing malpractice and really misleading if they kept that old naming scheme. You can thank Samsung for this since they were the first ones to operate in bad faith.

When Intel’s 14nm first released, Morris Chang of TSMC insisted they name their competing FinFet node 16nm since by his own admission they were behind. Then Samsung swooped in to take the marketing win by naming their competitor 14nm despite it performing worse than Intel’s & TSMC’s nodes. Thus the arm’s race of node naming schemes began.

Mainly wccftech, which still thinks Intel 4 is equal to TSMC 7nm & Intel 20A is equal to TSMC 5nm. Just check the site.

 

[DrMrLordX]

don't mind him, he huffs and puffs from time to time.

Only when I'm right.

Intel 3 seems healthy

Surprising if true. Considering that Intel 4 isn't even on the market yet. Unless Intel relaxed their yield and performance targets, of course.

This drives me absolutely crazy when the media does this:

It drives me crazy when they DON'T do that.

 

[mikk]

I think it must include some compute die. None of the other dies are likely to be 20A.

He is talking about the chip and not just a specific tile. For obvious reasons only the compute tile gets 20A.

 

[H433x0n]

It drives me crazy when they DON'T do that.

So you genuinely believe that 18A (a node that has proper backside power delivery and GAAFet) would be analogous to TSMC’s N5? That the N4 minor refresh that is only 6% more dense from the original N5 will outperform 18A? I mean, after all it’s supposed to be labeled 5nm+ so clearly N4 would be 20% better.

On that note, do you think it was appropriate that TSMC labeled their N5 refresh N4 with such a tiny change in performance?

Going by TSMC’s naming metrics, the node that RPL-R is shipping with should be called Intel 6. The node performance improvements from Tiger Lake -> RPL-R is probably double what TSMC got from N7->N6.

 

[SiliconFly]

So you genuinely believe that 18A (a node that has proper backside power delivery and GAAFet) would be analogous to TSMC’s N5? That the N4 minor refresh that is only 6% more dense from the original N5 will outperform 18A? I mean, after all it’s supposed to be labeled 5nm+ so clearly N4 would be 20% better.

On that note, do you think it was appropriate that TSMC labeled their N5 refresh N4 with such a tiny change in performance?

Going by TSMC’s naming metrics, the node that RPL-R is shipping with should be called Intel 6. The node performance improvements from Tiger Lake -> RPL-R is probably double what TSMC got from N7->N6.

Ur right. There are people out there who want to label Intel 18A as 5nm & make it look like it's a TSMC 5nm equivalent.