Discussion Intel current and future Lakes & Rapids thread

[adroc_thurston]

What would they be if not final performance projections?

They are.
ARL is no good at high power.

 

[H433x0n]

What would they be if not final performance projections? It would make little sense to compare an ES to a prior generation. You'd generally want a metric like %target in that case.

It’s KPI for first silicon - nothing more, nothing less.

I’m not promising anything crazy, for all I know performance doesn’t improve from the IgorsLab data. It’s not a final performance projection though, it’s a KPI at an early milestone.

 

[DrMrLordX]

Under the old naming scheme, Intel 3 would be 7++, 20A would be 5nm, and 18A would be 5+. But kind of pointless to insist on those names at this point.

If you read the Tom's article @SiliconFly linked, Tom's calls Intel 3 "previously 5nm". So I actually don't think they would have used a plus monicker for it. If that had been the case then 20a would have been 5nm, not 18a in any case.

Regardless for those nodes that had former names (which 20a and 18a did not), it's quite helpful for honest journalists to occasionally remind people of their original name so that they can be approximately judged in relation to Intel nodes under the old naming scheme. Which is something Intel marketing very much doesn't want from journalists. So when someone comes on the forums and actually gets upset at Tom's Hardware (or anyone else) from not taking the bait from Intel and just calling Intel 3 a 3nm node it kind of makes you wonder.

On a side note, thinking about all this in juxtaposition to the recent Arrow Lake v Raptor Lake 250W slide that was leaked and the fact that Intel has pushed off High NA EUV, it kind of makes me wonder . . .

I think she was the second person under Murphy and when Bob Swan kicked Murphy out she got promoted.

Uh, you mean Murthy? Venkata “Murthy” Renduchintala?

 

[H433x0n]

They are.
ARL is no good at high power.

You’re way too confident. People inside the building aren’t even as confident as you are with many of your proclamations.

There’s a lot of uncertainty with ARL for a multitude of reasons, so when you say things like this it makes me doubt everything you say.

LNC is the first core developed with a properly defined PDK. It’s the first major core developed to be fabricated outside of the building as well. Previous arch like Golden Cove & Redwood Cove, Sunny Cove were developed with a heavier emphasis on internal tools / processes with a heavy reliance on vertical integration. These cores couldn’t even be fabricated using an external fab without porting the IP. The only thing that anybody has reasonable confidence in is that ARL won’t end up like MTL and slip a year or 2 behind schedule.

 

[adroc_thurston]

You’re way too confident

Well I mean, Intel gives pretty clear pre-Si projections so how could I doubt Intel itself?

There’s a lot of uncertainty with ARL for a multitude of reasons

There is none.
Pretty simple product.

The only thing that anybody has reasonable confidence in is that ARL won’t end up like MTL and slip a year or 2 behind schedule.

It's literally a compute tile swap.
Pretty hard to let that slip.

 

[H433x0n]

If you read the Tom's article @SiliconFly linked, Tom's calls Intel 3 "previously 5nm". So I actually don't think they would have used a plus monicker for it. If that had been the case then 20a would have been 5nm, not 18a in any case.

Regardless for those nodes that had former names (which 20a and 18a did not), it's quite helpful for honest journalists to occasionally remind people of their original name so that they can be approximately judged in relation to Intel nodes under the old naming scheme. Which is something Intel marketing very much doesn't want from journalists. So when someone comes on the forums and actually gets upset at Tom's Hardware (or anyone else) from not taking the bait from Intel and just calling Intel 3 a 3nm node it kind of makes you wonder.

On a side note, thinking about all this in juxtaposition to the recent Arrow Lake v Raptor Lake 250W slide that was leaked and the fact that Intel has pushed off High NA EUV, it kind of makes me wonder . . .

source

It’s right here in this anandtech article. Tom’s Hardware is just flat out wrong.

 

[DrMrLordX]

It’s right here in this anandtech article. Tom’s Hardware is just flat out wrong.

I see Intel's slide explaining the renames. What exactly is wrong with the Tom's article? Anandtech's writer (Dr. Cutress no less) asserts that Intel 3 was Intel 7nm+, but that's just one tech writer contradicting the other. The Intel slide does not list a former name for Intel 3.

Meanwhile here's a Hardware Times article that agrees with the sentiment that Intel 3 used to be Intel 5nm:

Intel Renames 10nm ESF Node to 7nm, 7nm to 4nm, 5nm to 3nm in Roadmap Update | Hardware Times

A while back it was rumored that Intel has planning to change its process node naming scheme to match the transistor densities of rival foundries such as TSMC and Samsung. Today at its Intel Accelerated event, the chipmaker did just that. The 10nm Enhanced SuperFin node which will power the...

www.hardwaretimes.com

In any case, what exactly are you arguing about? Intel never called 18a 5nm or anything else.

 

[Abwx]

It’s KPI for first silicon - nothing more, nothing less.

I’m not promising anything crazy, for all I know performance doesn’t improve from the IgorsLab data. It’s not a final performance projection though, it’s a KPI at an early milestone.

Why would they do marketing slides for early silicon..?..

To enbold their enginers..?.

 

[H433x0n]

I see Intel's slide explaining the renames. What exactly is wrong with the Tom's article? Anandtech's writer (Dr. Cutress no less) asserts that Intel 3 was Intel 7nm+, but that's just one tech writer contradicting the other. The Intel slide does not list a former name for Intel 3.

Meanwhile here's a Hardware Times article that agrees with the sentiment that Intel 3 used to be Intel 5nm:

Intel Renames 10nm ESF Node to 7nm, 7nm to 4nm, 5nm to 3nm in Roadmap Update | Hardware Times

A while back it was rumored that Intel has planning to change its process node naming scheme to match the transistor densities of rival foundries such as TSMC and Samsung. Today at its Intel Accelerated event, the chipmaker did just that. The 10nm Enhanced SuperFin node which will power the...

www.hardwaretimes.com

In any case, what exactly are you arguing about? Intel never called 18a 5nm or anything else.

Source

The remaining two entries on the roadmap, 'Intel 3' and 'Intel 20A' represent what intel previously branded as 7+ and 5nm, respectively.

Here’s your beloved Tom’s Hardware saying Intel 3 was to be called “7nm+”.

Intel 3 / 4 were previously considered the same node before the rename (they sort of still are the same node really), with 3 just being optimizations on the existing IP.

 

[H433x0n]

Why would they do marketing slides for early silicon..?..

To enbold their enginers..?.

It was never marketing slides made for public consumption. It’s meant as a progress report to assess where things are at each stage.

 

[Abwx]

It was never marketing slides made for public consumption. It’s meant as a progress report to assess where things are at each stage.

More likely for OEMs comsumption, i dont think that an Intel employee would give access to internal infos, but someone who is tied to Intel could do so.

As such it s not how work is in progress, OEMs do not need non confirmed specs, that s likely what are the projected perfs once the silicon is done right, eventually they are not at this perfs level with early silicon.

 

[Khato]

Why would they do marketing slides for early silicon..?..

To enbold their enginers..?.

This assumes that the 'marketing slides' on the Igor's Lab article came directly from the leak. The data may well be legitimate, but the lack of any Intel logo or confidential marking is pretty clear evidence that the graphs themselves were most likely produced by Igor's Lab.

 

[Abwx]

This assumes that the 'marketing slides' on the Igor's Lab article came directly from the leak. The data may well be legitimate, but the lack of any Intel logo or confidential marking is pretty clear evidence that the graphs themselves were most likely produced by Igor's Lab.

I would think that he made things such that the source cannot be identified, one never know...

However, I have been given internal performance projections that are supposed to forecast the performance of a current Core i9-13900K with the appropriate models of Raptor Lake Refresh and Arrow Lake. Since this is not public PR material, these projections can certainly be considered realistic, even though the finished CPU could of course perform differently. But at least it is more than just a rough benchmark.

Intel’s internal performance projection for Raptor Lake S Refresh and Arrow Lake S - How fast the CPU and iGP are expected to be | Exclusive | igor´sLAB

The Raptor Lake refresh is expected to arrive this year as the 14th CPU generation for the desktop. But the real successor, Arrow Lake-S for desktop, is also increasingly materializing along with the…

www.igorslab.de

 

[Exist50]

It’s KPI for first silicon - nothing more, nothing less.

Granted, I'm not familiar with how Intel in particular presents its data internally, but nothing in that diagram indicates to me that it's a comparison of early silicon. No remark about the stepping or ES milestone, no actual numbers, no comparison to targets, etc. That's the kind of slide you'd see presented to partners, or maybe sufficiently removed execs.

If you read the Tom's article @SiliconFly linked, Tom's calls Intel 3 "previously 5nm".

Tom's is wrong. Simple as that. Intel 3 is an enhanced version of Intel 4, not a full node shrink.

If that had been the case then 20a would have been 5nm, not 18a in any case.

Yes, 20A would indeed be called 5nm under Intel's old naming convention.

it's quite helpful for honest journalists to occasionally remind people of their original name so that they can be approximately judged in relation to Intel nodes under the old naming scheme

To what end? The names tells us effectively nothing of the node characteristics, and in most cases, using the old naming would make comparisons vs TSMC and Samsung (which is realistically what more people care about) less accurate. At this point, it just creates unnecessary confusion to use those names, and it's even worse when they can't even be bothered to get them right.

Granted, I don't like Intel 3's name vs TSMC N3, but it'll probably even out again around N2 vs 18A.

Meanwhile here's a Hardware Times article that agrees with the sentiment that Intel 3 used to be Intel 5nm:

Hardware Times is a rag. Not even worth the effort to type that out.

 

[trexfromouterspace]

And while AMD has iterated a lot on Zen 1, they even changed many of the underlying "lego blocks" in Zen 3, they kept the overall design still surprisingly close to the original:

Zen 3 has no relationship to Zen 1, it's a fully from scratch architecture designed by a different team. It had a similar bounding box in terms of width/size, but the internals are completely different.

 

[Thunder 57]

Zen 3 has no relationship to Zen 1, it's a fully from scratch architecture designed by a different team. It had a similar bounding box in terms of width/size, but the internals are completely different.

I would have to disagree. There are plenty of similarities. If anything, I'd say Zen 2 was more different from Zen 1 than Zen 2 and Zen 3.

 

[adroc_thurston]

There are plenty of similarities

you can literally look up labeled Zen2 and Zen3 CCD annotations.
The cores are very-very different.

 

[Thunder 57]

you can literally look up labeled Zen2 and Zen3 CCD annotations.
The cores are very-very different.

OK. Zen 3 had eight cores in a CCD. Zen 2 introduced the the chiplet architecture, changed the branch predictor, and revised the cache to reduce the L1 inscruction to increase the uOP cache. Seems like a lot of change.

 

[adroc_thurston]

Zen 2 introduced the the chiplet architecture

That's not core.

changed the branch predictor

That was actually pulled in from Zen3 cadence.

and revised the cache to reduce the L1 inscruction to increase the uOP cache

That's relatively minor changes (see ARM cores having configurable L1$'s and all).
Zen3 was shiny new and you only have to look at the cores physically to get it.
Totally different layout.

 

[Thunder 57]

That's not core.

That was actually pulled in from Zen3 cadence.

That's relatively minor changes (see ARM cores having configurable L1$'s and all).
Zen3 was shiny new and you only have to look at the cores physically to get it.
Totally different layout.

But they brought into Zen 2. I guess we just have to disagree.

 

[SpudLobby]

https://twitter.com/x/status/1684849297588953089

So apparently, it might be ARL-U's compute tile on 20A, not ARL-S or a desktop part, and obviously we know Lunar Lake is not on 20A or 18A with very high confidence now.

If true, this is actually fairly good news for the relative confidence Intel have in 20A and 18A and/or ARL-U at least in terms of the midrange efficiency and performance, it would've been much worse had 20A tiles been restricted to the desktop (which also doesn't make any sense given clockspeed concerns or die area of the top SKUs on a new process), and N3 for LNL makes more sense as well.

I think ARL's top performance will be meh, and it's likely they have a litany of issues, those performance projections at high power draw look pretty lame, but it remains to be seen what their midrange performance/efficiency improvements bring in ARL (at e.g. modest clocks).

 

[H433x0n]

Granted, I'm not familiar with how Intel in particular presents its data internally, but nothing in that diagram indicates to me that it's a comparison of early silicon. No remark about the stepping or ES milestone, no actual numbers, no comparison to targets, etc. That's the kind of slide you'd see presented to partners, or maybe sufficiently removed execs.

I don’t have a direct line to client, so I acknowledge I’m not the best source for ARL info. Internally, there’s nothing that lines up with it. I was told it’s likely to be extrapolated from an early KPI.

I suspect it’s an estimate given to partners, this estimate is below design goals though so I don’t know how to square that.

 

[Exist50]

So apparently, it might be ARL-U's compute tile on 20A, not ARL-S or a desktop part, and obviously we know Lunar Lake is not on 20A or 18A with very high confidence now.

I don't think that's what Bionic is saying. He seems to be implying ARL-U is neither N3 nor 20A. Which could square with some previous rumors of it being essentially a MTL-U refresh on Intel 3.

 

[Doug S]

Isn't the biggest news here "running on its first stepping"?

When's the last time that's been true for any Intel CPU? In the past they never did the level of simulation that e.g. Apple and AMD do, because when you control your fabs you can push hot lots through as often as you like, since there are no other customers to upset. So why waste all that effort on simulation when you can run on real silicon if you're willing to wait a bit? Perhaps they are changing their ways and adapting to the times.

 

[Exist50]

Isn't the biggest news here "running on its first stepping"?

When's the last time that's been true for any Intel CPU? In the past they never did the level of simulation that e.g. Apple and AMD do, because when you control your fabs you can push hot lots through as often as you like, since there are no other customers to upset. So why waste all that effort on simulation when you can run on real silicon if you're willing to wait a bit? Perhaps they are changing their ways and adapting to the times.

I sincerely doubt they're going to be shipping on A-step. It's just what they're testing with for now. Honestly, if LNL ships on B-step, that would be an accomplishment by Intel standards.