Discussion Intel current and future Lakes & Rapids thread

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nicalandia

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Jan 10, 2019
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The 32 core presumably has much higher base clock.

Will say that when it comes to Sapphire Rapids, I wouldn't assume that a model even with a set SKU will actually make it to market.
There is a Zero Chance that Intel will release such CPU, just to be trampled by AMD Zen3 5995WX..
 

jpiniero

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There is a Zero Chance that Intel will release such CPU, just to be trampled by AMD Zen3 5995WX..
It'd still be better than what they have now. Right now, all of Dell's Xeon branded workstations are still 14 nm. And you know Dell is Intel's BFF.
 

nicalandia

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Except the Xeon will have dual AVX-512 units and the 5995WX lacks those. Intel has a window of opportunity till Zen 4 HEDT launches.
Not with lowly 32C/36T it will not make any difference. I mean 64C/128T AVX-256 vs 32C/64T AVX-512 will be pretty even, I will check the benchmarks posted so far.

Thats on AVX-512 about even, but the rest will be just too much of a core disparity.
 

nicalandia

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Very low yields for Sapphire Rapids.


So about 34 to 40 Fully functional dies per wafer.
FdxIqhXXgAAfA2N.jpeg
 

jpiniero

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Very low yields for Sapphire Rapids.

Shocking, shocking development. Actually 50-60% being usable would be better than I expected but who knows how far down they are cutting to get to 50-60% though.
 

Kocicak

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Jan 17, 2019
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That is another half a year of delay to hopefully fix the production process to be usable for these products? I guess they have time for a few more steppings now. Once ready, these CPUs should be really good and reliable. That is good news... :)
 

nicalandia

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Shocking, shocking development. Actually 50-60% being usable would be better than I expected but who knows how far down they are cutting to get to 50-60% though.
So they get 68 full sized dies out of the whole 300mm wafer. the partial dies are not functional and are discarded. Out of those 68 only 34-40 are still functional(some dies will have minor defects that will just be a lower tier CPUs with lower cores)

So let's say that Intel spends about $3,000 per wafer(As per Dr. Ian Cutress estimate of 1/3 cost for Intel as opposed to TSMC Cost of $10,000 per finished wafer), that would mean that each fully functional die is about $75-88 per piece. That is still not that much and Intel can just keep "Printing" more of them.

The issue would be how fast can they ramp up production?
 
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nicalandia

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That's funny. I was told the delays weren't yields but bugs with the design . . .
It's really the Whole Enchilada...! Lower Yields and Bugs that are compounding the issue. more than 13 Steppings is something really unheard of before.
 

nicalandia

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Hitman928

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So they get 68 full sized dies out of the whole 300mm wafer. the partial dies are not functional and are discarded. Out of those 68 only 34-40 are still functional(some dies will have minor defects that will just be a lower tier CPUs with lower cores)

So let's say that Intel spends about $3,000 per wafer(As per Dr. Ian Cutress estimate of 1/3 cost for Intel as opposed to TSMC Cost of $10,000 per finished wafer), that would mean that each fully functional die is about $75-88 per piece. That is still not that much and Intel can just keep "Printing" more of them.

The issue would be how fast can they ramp up production?
Are you taking into account that it takes 4 dies for a SPR CPU? There will also be assembly/packaging costs with yield losses in packaging as well.
 

LightningZ71

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For the peanut gallery, the previous post's "vs fastest Genoa" test is a 2P 112 core Saphire Rapids vs. a 96 core 1P Genoa system. The 1P Genoa system is roughly equivalent to the SPR system in MT. A 2P system, assuming no major power constraints, would be markedly faster in MT in almost every subtest, save for AES...
 

LightningZ71

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No, 40 fully functional dies means that they can then attempt to package 10 CPUs at 60% lithography yield. This says nothing about their packaging success rate, which we know will not be 100% if industry history is to be believed. It is highly likely that packaging will cost them a few percent more losses in start to finish yield.
 

nicalandia

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For the peanut gallery, the previous post's "vs fastest Genoa" test is a 2P 112 core Saphire Rapids vs. a 96 core 1P Genoa system. The 1P Genoa system is roughly equivalent to the SPR system in MT. A 2P system, assuming no major power constraints, would be markedly faster in MT in almost every subtest, save for AES...
Fastest Single Thread Performance posted so far.

There is another entry where the MT is 78,000 points but the ST is 36% lower

 

Kocicak

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"Functional" does not mean meeting some other perf. (quality) goals of the silicone. It may not be able to perform in required power envelope etc.
 

LightningZ71

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It could be geekbench... or it could be the overhead from Intel's layout of the 4 CPU die and the fabric extensions between them. We know from previous generations that Intel's fabric for their Xeon scalable architecture imposes a non-trivial amount of overhead on MT performance. It may scale gracefully in some ways, but, there's still a hit to MT performance that exists. This isn't implying that AMD's method is perfect, but it seems to serve them well so far.

Another possibility is that, in single core situations, SPR can stretch it's legs a bit on that single core and run at a higher clock and power level than it can when all cores are active. We do note that the related P cores in ADL/RPL can consume quite a lot of power when left to run without limits. Zen4 doesn't seem to draw quite as much and I speculate that when all 96 cores are running on Genoa, they are able to maintain higher performance due to their efficiency.
 

nicalandia

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"Functional" does not mean meeting some other perf. (quality) goals of the silicone. It may not be able to perform in required power envelope etc.
Fully Functional Dies does not mean that All of them will be Top Quality Silicon for sure, but they can be lower tier SKUs, but they are functional enough to be included on the successful yield rate, otherwise the yield rate is just lowered.
 

Exist50

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Very low yields for Sapphire Rapids.


So about 34 to 40 Fully functional dies per wafer.
View attachment 70166
If yields were actually the problem, why would they only delay the launch of the MCC die, which has ~half the silicon of a full XCC package? And why would those yield issues not apply to ICL-SP, ADL, RPL, etc? And how would a single quarter be enough to materially change them? There's a lot of things that make no sense here.

An alternative explanation would be that Intel's doing a staggered launch between the dies, just as they typically do. Then, a few weeks would be expected.

I also find this kind of funny in regards to the insistence a few months ago (originally from Kuo, not TrendForce, I'll note) that SPR ramp (everything) was delayed to H2'23.
 

Kocicak

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Fully Functional Dies does not mean that All of them will be Top Quality Silicon for sure, but they can be lower tier SKUs, but they are functional enough to be included on the successful yield rate, otherwise the yield rate is just lowered.
That still can mean some mismatch between the silicone you need to build the SKUs you would like to sell and the silicone that comes out of the foundry.

You may be getting 60% functional chips, but when you need half of them to be high quality and you are getting just 10%, you still have a big problem, because it severely limits the number of some SKUs you can ship.

I have a suspition that something like this may be happening too, because otherwise Intel would not announce such a big delay again and they would try to at least make some CPUs. EDIT: I believe that they did not announce it yet officially?
 
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Doug S

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Charlie had an article yesterday about SPR's successor, Emerald Rapids. He said Intel still maintains it will come around a year after SPR, but I wonder how much of that is "we need SPR on the market long enough to make all this worth it" versus "Emerald Rapids is trouble plagued too so that number is just a hope and a dream".

If Emerald Rapids really is a year away today they should have a good idea of how well it is working, and if things are going well at some point it makes sense to throw in the towel on SPR and concentrate all your resources on pulling in Emerald Rapids a quarter or two instead.
 

Markfw

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