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Discussion Intel current and future Lakes & Rapids thread

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Doug S

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Note that these numbers were presented (among others) in a ~2016 talk so these should have been pre-order numbers before the process landed. I'd suspect that is closer to "new" than "fully depreciated".

@ repoman27: The gates used for the cost estimate is "Actual used gates/mm2" (or rather "gates/wafer" which is that multiplied by ~63630 , probably the wafer area) which is "gates/mm2 * Gate Utilization * Parametric yield impact".

Not sure what drives gate utilization (maybe heat density?) but parametric yield utilization is yield that doesn't consider defects (i.e. catastrophic failures) but considers process variations that cause some elements to perform worse than required.

One question with parametric yield is how often that results in unusable chips vs. just chips that you would sell with a lower bin (e.g. worse clock speed) or with the problematic parts of the chip disabled (just as you do with defects).

Well those numbers conflict greatly with those seen in other sources. Why should I believe this source over those others?
 

uzzi38

Golden Member
Oct 16, 2019
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Well those numbers conflict greatly with those seen in other sources. Why should I believe this source over those others?
With the exception of Marvell's, they're all estimations. Marvell's are likely accurate for mid-2020 figures, but I wouldn't assume costs have drastically fallen since. N7 is still a rather highly sought after node and TSMC have increased their prices since (albeit not by much to most of the bug customers, the rise is likely going to be enough to cancel out most of the improvements).

Frankly speaking there's not really any reason to trust any of the other estimates over each other.
 

IntelUser2000

Elite Member
Oct 14, 2003
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I doubt the semi industry really cares much about node price increases when the forced lockdowns and laying off of people causing supply chain issues are contributing to price increases in every area. We might be hyper focused about computer chips here, but nearly every category is affected.

The prices are not going down until the two factors are resolved, which I don't believe will happen anytime soon and I mean by years.

That means more profits and revenue for those companies, which will dwarf cost increases.

Hey the house and your family inside are burning but at least you are warm for a while right?
 

IntelUser2000

Elite Member
Oct 14, 2003
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I don't subscribe to the theory Arrowlake would have 256EUs on one die and 64EUs on the other die, Foveros or not. Strange configurations usually happen for a reason but sometimes they happen because it's convenient. Like layout reasons.

I speculated for a while that the 1.25MB cache in Tigerlake was special but it was just likely layout related. Nothing special about that cache other than fitting much as they could.

@repoman27 I don't get why you only count the EUs in your die size calculation for the iGPU. You need to count for the whole block. I remember Tigerlake's 96EU iGPU was almost 45mm2. Here's a good annotation: https://cdn.mos.cms.futurecdn.net/m22pkncJXbqSMVisfrWcZ5-1200-80.jpg

The one it's called "bunch of other stuff" is the fixed function units that cannot be avoided and needs to increase if performance is to scale beyond 96EUs.* Even the L3 cache portion(which scales poorly with latest processes) will need to increase to compensate for the bandwidth requirements.

There's nothing that says it's the 96EU die or something. Just like they won't only have a 2+8 die because it's the only one floating out there. They know how to proliferate countless different die configurations.

*Intel could do this but don't expect performance to follow. Look at Ampere. Nvidia purposely decided to ramp up shader counts without similar increases in TMUs and ROPs. That's why it performs less than Flops ratings. Maybe call it marketing units?
 

andermans

Member
Sep 11, 2020
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With the exception of Marvell's, they're all estimations. Marvell's are likely accurate for mid-2020 figures, but I wouldn't assume costs have drastically fallen since. N7 is still a rather highly sought after node and TSMC have increased their prices since (albeit not by much to most of the bug customers, the rise is likely going to be enough to cancel out most of the improvements).

Frankly speaking there's not really any reason to trust any of the other estimates over each other.
I doubt Marvell's numbers are that accurate. As said they're the same numbers from that ~2016-2017 presentation so they are 3-4 years out of date. They're only that accurate for 2020 if things didn't really change since then.

(also as a side-note is that nobody says TSMC or any vendor really. It could all be samsung or GF's canceled process)
 

NostaSeronx

Diamond Member
Sep 18, 2011
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From 2019:
IBS2019.png

However, it uses completely different metrics...
::Wafer cost divided by net die = die cost, divided by billions of transistors given to that node = cost of billion transistors.

It also uses an extrapolated design cost metric on top of the wafer cost. If anyone was wondering why the wafer costs are expensive compared to other sources. Essentially the cost to do a ~100mm2 design is added on top.

Also @andermans:
10nm/7nm ~0.1 defect density and 5nm sub-~0.1 defect density
TSMC 5nm Yield ASML.jpg
 
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andermans

Member
Sep 11, 2020
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From 2019:
View attachment 53625

However, it uses completely different metrics...
::Wafer cost divided by net die = die cost, divided by billions of transistors given to that node = cost of billion transistors.

It also uses an extrapolated design cost metric on top of the wafer cost. If anyone was wondering why the wafer costs are expensive compared to other sources. Essentially the cost to do a ~100mm2 design is added on top.

Also @andermans:
10nm/7nm ~0.1 defect density and 5nm sub-~0.1 defect density
View attachment 53626
Interesting, seems like the source is the same as previously (International Business Strategies) but a different year. I would hope that they at least be internally consistent with each other, but hard to believe that here. (Hard to explain the increased wafer prices for 16/10nm in 2016->2019)
 

repoman27

Member
Dec 17, 2018
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I don't subscribe to the theory Arrowlake would have 256EUs on one die and 64EUs on the other die, Foveros or not. Strange configurations usually happen for a reason but sometimes they happen because it's convenient. Like layout reasons.

I speculated for a while that the 1.25MB cache in Tigerlake was special but it was just likely layout related. Nothing special about that cache other than fitting much as they could.

@repoman27 I don't get why you only count the EUs in your die size calculation for the iGPU. You need to count for the whole block. I remember Tigerlake's 96EU iGPU was almost 45mm2. Here's a good annotation: https://cdn.mos.cms.futurecdn.net/m22pkncJXbqSMVisfrWcZ5-1200-80.jpg

The one it's called "bunch of other stuff" is the fixed function units that cannot be avoided and needs to increase if performance is to scale beyond 96EUs.* Even the L3 cache portion(which scales poorly with latest processes) will need to increase to compensate for the bandwidth requirements.

There's nothing that says it's the 96EU die or something. Just like they won't only have a 2+8 die because it's the only one floating out there. They know how to proliferate countless different die configurations.

*Intel could do this but don't expect performance to follow. Look at Ampere. Nvidia purposely decided to ramp up shader counts without similar increases in TMUs and ROPs. That's why it performs less than Flops ratings. Maybe call it marketing units?
Sorry, my measurements did include more than just the EUs.

You can see clearly from that TGL 4+2 LP die shot that Intel has already laid out the Gen12 GPU to accommodate exactly the type of disaggregation I was speculating about. The fixed function blocks, ring agent, etc. is on the left (labeled "A bunch of stuff"). None of that needs to scale with EU count—you don't need additional ring stops or HEVC/VP9 encoders/decoders to support additional EUs. In the middle is a block of 64 EUs along with TMUs, cache, etc.—everything you do need to scale up. To the right is a second block of 32 EUs along with supporting structures.

Now, chop the die right at the prominent division between the two EU blocks (along the FIVR line). The SoC tile retains all of the fixed function "stuff" as well as a fully functional 64 EU GT1 GPU. Intel can then fab a 128 EU GPU tile on TSMC N3 and use Foveros to tack it back on. You end up with an SoC design that can support 64 EU GT1/desktop SKUs, 192 EU GT2/notebook SKUs, and with the addition of a second GPU tile, a 320 EU GT3/Arrow Lake configuration. Move some of the L3$ to the Foveros base tile, and you've got a solution that is almost ideal from a disaggregation standpoint.
 

repoman27

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Dec 17, 2018
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Interesting, seems like the source is the same as previously (International Business Strategies) but a different year. I would hope that they at least be internally consistent with each other, but hard to believe that here. (Hard to explain the increased wafer prices for 16/10nm in 2016->2019)
Not to drag on about this too much longer, but I was looking over the IBS paper that included the chart that was in Ian's video, and noticed a few things.

"Wafer cost ($)" is their estimate for "TOTAL Yielded wafer cost", which applies a "Line yield (%)". Once again, no mention of specific foundry, process, projected D0, or yield model used. Also those wafer costs do not include TSMC's substantial margin, so they are not directly comparable to the "Foundry sale price per wafer" from the CSET paper. You'd have to multiply IBS's "Depreciation" figure by 4 to get similar numbers to the CSET calculations. In the case of 16/14nm FinFET that would work out to a "Foundry sale price per wafer" in Q4'16 of $9,242.

The footnotes for the version of that table from the most recent IBS white paper, dated June 2016, are as follows:
Note:
* 90nm, 65nm, 45/40nm, 28nm, and 20nm are in two years of high-volume production.
* 16/14nm is in Q4/2016, 10nm is in Q4/2017, and 7nm is in Q4/2018.
The upward trend in "Cost per 100M gate ($)" only includes 20nm and the authors future projections. If memory serves me, TSMC's only 20nm node was 20SOC, which was primarily used by Apple for the A8/A8X.
 
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Doug S

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"Wafer cost ($)" is their estimate for "TOTAL Yielded wafer cost", which applies a "Line yield (%)". Once again, no mention of specific foundry, process, projected D0, or yield model used. Also those wafer costs do not include TSMC's substantial margin, so they are not directly comparable to the "Foundry sale price per wafer" from the CSET paper. You'd have to multiply IBS's "Depreciation" figure by 4 to get similar numbers to the CSET calculations. In the case of 16/14nm FinFET that would work out to a "Foundry sale price per wafer" in Q4'16 of $9,242.

OK I can totally buy that the lower number is a snapshot in time of TSMC's production cost and the higher number we've seen is TSMC's asking price which includes their margin.
 

eek2121

Golden Member
Aug 2, 2005
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OK I can totally buy that the lower number is a snapshot in time of TSMC's production cost and the higher number we've seen is TSMC's asking price which includes their margin.
The number I've seen floating around in the past 2 years was between $10,500 and $11,000 for N7, and around $18,000 for N5 for what it's worth. These were from decently old leaks from a large volume customer (that we never found out the name of). Every time this comes up, the numbers drift back in that direction. I believe the last number I saw was $10,818 for N7. I don't remember the exact N5 number. Add in a 10% increase due to the supply chain and inflation nonsense and you land at about $11,900 or so for N7. The defect rate of N7 was listed as being under 8%, which means > 92% of dies were defect free. N6 and N5 apparently have an even better defect rate.

I do not know the accuracy of these numbers, of course, but my gut tells me they are close to correct for a large-ish customer.
 
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repoman27

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Dec 17, 2018
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The number I've seen floating around in the past 2 years was between $10,500 and $11,000 for N7, and around $18,000 for N5 for what it's worth. These were from decently old leaks from a large volume customer (that we never found out the name of). Every time this comes up, the numbers drift back in that direction. I believe the last number I saw was $10,818 for N7. I don't remember the exact N5 number. Add in a 10% increase due to the supply chain and inflation nonsense and you land at about $11,900 or so for N7. The defect rate of N7 was listed as being under 8%, which means > 92% of dies were defect free. N6 and N5 apparently have an even better defect rate.

I do not know the accuracy of these numbers, of course, but my gut tells me they are close to correct for a large-ish customer.
Those numbers are too high.

For the past 18 months, the most widely cited numbers for TSMC's wafer prices have been sourced from a research paper published in April 2020 by Georgetown University's Center for Security and Emerging Technology (CSET) and authored by Saif M. Khan and Alexander Mann. The full document is available here: https://cset.georgetown.edu/publication/ai-chips-what-they-are-and-why-they-matter/

The following chart is located in "Appendix D: Chip Economics Model":



Being an academic research paper, the authors were very forthright with disclosure regarding the methodology of their cost model. Saif Khan, the primary author, has also joined forum discussions to further clarify the source of the numbers, weigh in on the pros and cons of their particular model, and attempt to establish the overall accuracy and/or suitability for use.

Scotten Jones of IC Knowledge, who has been working on what is arguably the best strategic cost and price model in the industry for 20 years, published a detailed follow-up at SemiWiki: https://semiwiki.com/semiconductor-manufacturers/tsmc/292760-leading-edge-foundry-wafer-prices/

The conclusion is:
This brings us to the key question, how accurate are the row 7 “Foundry sale price per wafer” values in the paper and the answer is not very. There is basically an error slope to the results with the 90nm prices being too low and at 5nm the prices are too high.
Your theory that prices would increase as a node matures is completely incorrect. The most significant contributor to wafer cost for a new node is capital depreciation. Because this is calculated as depreciation divided by wafer-outs per node per quarter, as the process ramps, utilization increases, and cycle times drop, you have a generally declining capital cost spread across a significantly higher number of wafers after the node reaches HVM. While TSMC will pocket some of that cost reduction to maintain their company wide 51% gross margin, as capacity expands, prices generally need to go down in order to keep utilization as high as possible. Even with continuing strong demand and pretty much every fab at full capacity, semiconductors are still extremely price sensitive components.

Defect density follows a curve that depends heavily on the maturity of the particular manufacturing process and cumulative number of wafer starts. It also shouldn't be a factor when it comes to foundry wafer pricing. Risk starts are called that for a reason, and generally that risk falls on the customer. TSMC tends to be somewhat forthcoming with their D0 numbers:




Yield percentage calculations depend heavily on the die size and method used to obtain them as well as the D0 at that particular time; you can't just quote a number for a wafer. Also, designs that take the expected defect density into account and make affordances for manufacturability can yield a significantly higher number of sellable dies.
 

Doug S

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Look at the capital depreciation figures on those CSET numbers. Those prices were from when N7 had already been pretty well depreciated and priced much lower than it cost when it was the latest node. No one was arguing that N7 sells for $15K or so now, only that it was when the node was new. They won't keep selling N5 wafers for $17K in a couple years when N3 is out, N7 will move even lower, etc.

Not that I believe those deprecation figures are necessarily accurate (i.e. they show it halting after five years) but in general that's a reasonable cost model.
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
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It was free access until a few minutes ago, they probably got spooked by a spike in traffic.

Turns out I had the page open still, so here's screenshots:
View attachment 53766

View attachment 53767
So unless you have Bapco results memorized for all CPU's, this is pretty much worthless.

If you could provide some other results to compare to , that would be great.
 
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Exist50

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So unless you have Bapco results memorized for all CPU's, this is pretty much worthless.

If you could provide some other results to compare to , that would be great.
I don't think the actual results hold much value so much as the fact that it's started showing up. Hopefully they can get it out closer to the summer this time. Certainly going to need any buffer they can get vs Zen 4.
 
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DisEnchantment

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Mar 3, 2017
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Man Intel grinding out new CPU families like no tomorrow.
Back when they were supplying us Silvermont, it was pulverizing J6 and i.MX like jelly.
Then we asked for a Airmont and future roadmaps, but they never bothered. They stood still but the world did not.
They shut down the delivery center that was supporting our R&D center back then and I took in some of the guys who were let go in our team.

I hope this will all click, while I don't like Pat's demeanor he does seem to have a great passion to restore Intel's glory and he seems to know what he is doing.
 

Markfw

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From his link, click "Performance Charts -> Crossmark Desktop". That leads you here, where you can click on any processor to see the details:
Thanks ! But thats not good news for Raptor lake. With the same thread count and more real cores than a 5950x, its 3/4 of the performance of a 5950x. 2082(5950x) vs 1591(Raptor)

Except something is wrong with these charts or benchmark. How can a 12600k beat a 5950x by 25% !!!!
 
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trivik12

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I agree. Key thing is we are already seeing benchmarks for RPL-S. Since they are planning 3 cpus in next 2 years they have to come lot sooner. We had RKT-S and ADL-S this year as well. Good for consumer if we will have more competitive Intel after being moribund for years.
 

dullard

Elite Member
May 21, 2001
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Thanks ! But thats not good news for Raptor lake. With the same thread count and more real cores than a 5950x, its 3/4 of the performance of a 5950x. 2082(5950x) vs 1591(Raptor)
I'm pretty sure that will change significantly in the next year before it's release. A year gives plenty of time to make significant changes (clock speeds, DDR5 5600 instead of the tested DDR5 4800, etc). If it truly was #438 out of 3561 chips tested in BAPCo, then Intel would never release it and would instead do an Alder Lake refresh.
 

jpiniero

Lifer
Oct 1, 2010
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I'm pretty sure that will change significantly in the next year before it's release. A year gives plenty of time to make significant changes (clock speeds, DDR5 5600 instead of the tested DDR5 4800, etc). If it truly was #438 out of 3561 chips tested in BAPCo, then Intel would never release it and would instead do an Alder Lake refresh.
Raptor Lake is an Alder Lake Refresh type chip. It's likely an ES with reduced clock speeds.
 

dullard

Elite Member
May 21, 2001
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Except something is wrong with these charts or benchmark. How can a 12600k beat a 5950x by 25% !!!!
It isn't a rendering benchmark. Rendering benchmarks are essentially just a measure of how many cores in a system. CrossMark uses more features of the chips. See pages 21 to 31 to see what affects the scores more and what affects it less (frequency > core count > drive speed > memory channels > graphics capabilities > memory capacity).

 
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