ZEN ES Benchmark from french hardware Magazine

[raghu78]

Lisa Su says " Our Ryzen processors at launch will have base clock speeds of 3.4 Ghz or higher" . The slide says 8C/16T and 3.4 Ghz+ , not 3.4 Ghz - . My interpretation is that the lowest base clock of 8C/16T Ryzen processors will be 3.4 Ghz. If there is a single 8C/16T SKU it could be base clock of 3.4 Ghz or higher. Alternatively we could have two 8C/16T SKUs with the slower 8C/16T at 3.4 Ghz and a faster flagship SKU at 3.6 Ghz. I am pretty sure the 6C/12T and 4C/8T SKUs will have even higher base clock speeds.

 

[swilli89]

Lisa Su says " Our Ryzen processors at launch will have base clock speeds of 3.4 Ghz or higher" . The slide says 8C/16T and 3.4 Ghz+ , not 3.4 Ghz - . My interpretation is that the lowest base clock of 8C/16T Ryzen processors will be 3.4 Ghz. If there is a single 8C/16T SKU it could be base clock of 3.4 Ghz or higher. Alternatively we could have two 8C/16T SKUs with the slower 8C/16T at 3.4 Ghz and a faster flagship SKU at 3.6 Ghz. I am pretty sure the 6C/12T and 4C/8T SKUs will have even higher base clock speeds.

Or it could mean that when they "launch" the high end SKU that they release is 3.4+ and then later then will release lower clocked versions.

 

[KTE]

Not at all, Ioff is a byproduct because such devices have lower transconductance and higher gate threshold voltage, hence a lower Ioff but that s not the main point for their usage.

Low power means low transconductance but as a consequence also lower switching capacitance, the end result is a device that has limited max frequency but wich is less power hungry at moderate frequencies.

Ioff is what GloFo/Samsung referred to in figures.

Its the lower voltage due to lower Ioff leakage thats a by-product enabling lower power.

It says right there from the horses mouth.

Sent from HTC 10
(Opinions are own)

 

[bjt2]

My issue was with the clocks, if anything with the info we have so far 3.4 should be the "slower" chips.

3.4Ghz base is already superior to INTEL's... Even higher? You want some user here and there to commit suicide?

 

[ecogen]

3.4Ghz base is already superior to INTEL's... Even higher? You want some user here to commit suicide?

Hey man, all I'm doing is reading 3,4+ as... you know.. 3,4+

I understand their concerns though, marketing doublespeak is used all the time. I just don't see the reason for all this negativity., at the end of the day before these leaks people were saying they were gonna be happy if zen reached SB IPC with halfway decent clocks.

 

[bjt2]

Hey man, all I'm doing is reading 3,4+ as... you know.. 3,4+

I understand their concerns though, marketing doublespeak is used all the time. I just don't see the reason for all this negativity., at the end of the day before these leaks people were saying they were gonna be happy if zen reached SB IPC with halfway decent clocks.

I was ironic... I was the guy who predicted 4GHz base...

 

[ecogen]

I was ironic... I was the guy who predicted 4GHz base...

I know the first part was a joke. Text really doesn't help with conveying tone.

 

[Phynaz]

So they will release 8C chips, after the initial launch that will be running at base clocks lower than even the old ES that was used in this review?

Depending upon parametric yield, sure, why not?

 

[Phynaz]

FO4 can be independent of IPC.

I have to ask, why are you so invested in FO4?

 

[prtskg]

I believed that zen won't reach BW IPC, seems like I was wrong. I believed that best zen chip (of 8 core) will have base frequency <= 3.2GHz, needless to say, I was wrong there too. I don't believe than zen can reach 5GHz on air, I really believe I'm right on this one. If I'm wrong here too, I'll be

 

[Fanatical Meat]

When should we expect:
A) More real but cherry picked benchmarks
B) Real benchmarks from reliable sources

 

[bjt2]

I have to ask, why are you so invested in FO4?

Keller said that Zen has the same DNA of bulldozer (and Jaguar), for me, since the best of BD was the high clock, this means only that Zen has low FO4 as bulldozer, because there are not other good thing in bulldozer...

FO4 is not related to IPC. If they appear to be correlated, it's only because of existing designs. But there is not any reason to forbid low FO4 and high IPC designs...

 

[DrMrLordX]

Also glofo's 14nm is IBM's finfet that will be used to make power9 but only uptil ~4GHz ranges .. I find these 5GHz@Air highly dubious.

Actually, GF has two 14nm processes, at least:

14nm LPP adapted from Samsung (with whatever modifications; we just don't know)

14nm HP adapter from IBM's team that was folded into GF. That process is more-or-less purpose-built for POWER9 and possible future IBM products.

How much IP sharing is there between the two processes? We don't know. I would expect POWER9 to go over 4 GHz sooner or later, though.

So they will release 8C chips, after the initial launch that will be running at base clocks lower than even the old ES that was used in this review?

Maybe at TDPs below 95W, sure.

When should we expect:
A) More real but cherry picked benchmarks
B) Real benchmarks from reliable sources

CES maybe?

 

[raghu78]

I believed that zen won't reach BW IPC, seems like I was wrong. I believed that best zen chip (of 8 core) will have base frequency <= 3.2GHz, needless to say, I was wrong there too. I don't believe than zen can reach 5GHz on air, I really believe I'm right on this one. If I'm wrong here too, I'll be

From the statements of a AMD overclocker buildzoid 5 Ghz on air is not realistically happening for 24x7. Maybe suicide runs.

https://www.reddit.com/r/Amd/comments/5krghq/remember_the_canard_pc_magazine_about_zen_it_has/?

buildzoid Extreme AMD Overclocker. 1580/2310 XFX RX 480 GTR 24 points 21 hours ago

" I'll just use this comment to say this since it's relevant to me.

I don't have a Zen but I know people who do.

I continue to stand by my comment about 5G not happening on air without too much voltage. This doesn't disprove the statement of ZenOC@Air=5G however I wouldn't get your hopes up because we don't know how many cores or volts actually managed that clock. (my sources never gave me absolute max clock just that it does about X.X for daily use)

For all those wondering about X.X. Well lets just say that I am pleased with X.X."

charlie of semiaccurate says Zen clocks well.

http://www.realworldtech.com/forum/?threadid=163466&curpostid=163829

"No hard data but friends have told me it clocks well. If 3.4 is launch speeds, 5 should be no problem for the pros. Haven't heard of any speed path issues yet but you never know until the LN2 guys get ahold of it.

-Charlie"

My guess is 4.5 Ghz now looks very realistic on air for 24x7. I think AMD will aim for max single core turbo of 4.2 Ghz with final release chips to remain competitive against Skylake and Kabylake in gaming.

 

[bjt2]

From the statements of a AMD overclocker buildzoid 5 Ghz on air is not realistically happening for 24x7. Maybe suicide runs.

https://www.reddit.com/r/Amd/comments/5krghq/remember_the_canard_pc_magazine_about_zen_it_has/?

buildzoid Extreme AMD Overclocker. 1580/2310 XFX RX 480 GTR 24 points 21 hours ago

" I'll just use this comment to say this since it's relevant to me.

I don't have a Zen but I know people who do.

I continue to stand by my comment about 5G not happening on air without too much voltage. This doesn't disprove the statement of ZenOC@Air=5G however I wouldn't get your hopes up because we don't know how many cores or volts actually managed that clock. (my sources never gave me absolute max clock just that it does about X.X for daily use)

For all those wondering about X.X. Well lets just say that I am pleased with X.X."

charlie of semiaccurate says Zen clocks well.

http://www.realworldtech.com/forum/?threadid=163466&curpostid=163829

"No hard data but friends have told me it clocks well. If 3.4 is launch speeds, 5 should be no problem for the pros. Haven't heard of any speed path issues yet but you never know until the LN2 guys get ahold of it.

-Charlie"

My guess is 4.5 Ghz now looks very realistic on air for 24x7. I think AMD will aim for max single core turbo of 4.2 Ghz with final release chips to remain competitive against Skylake and Kabylake in gaming.

Remember AMD statement of same energy/cycle as XV (namely same clock at same power). FX8370E, that is worse than XV in efficiency, reached 3.3/4.3 at 95W. Base clock was already promised >=3.4GHz... So I bet that we can hope of turbo max (1 core) of at least 4.4Ghz. Plus the auto OC feature that will push clock further...

 

[zinfamous]

Lisa Su says " Our Ryzen processors at launch will have base clock speeds of 3.4 Ghz or higher" . The slide says 8C/16T and 3.4 Ghz+ , not 3.4 Ghz - . My interpretation is that the lowest base clock of 8C/16T Ryzen processors will be 3.4 Ghz. If there is a single 8C/16T SKU it could be base clock of 3.4 Ghz or higher. Alternatively we could have two 8C/16T SKUs with the slower 8C/16T at 3.4 Ghz and a faster flagship SKU at 3.6 Ghz. I am pretty sure the 6C/12T and 4C/8T SKUs will have even higher base clock speeds.

See, I bolded the part that everyone is kinda glossing over. She said at launch. They are likely launching their top, maybe even only the mid-binned chips at first. Grammatically, using only this sentence, it is perfectly reasonable to assume that there very well could be some lower-clocked chips arriving after launch for more mainstream cheaper applications. Many are willing to accept the + part has even higher base clocks--sure, why not? But why ignore that chips can certainly be released after initial launch at lower clocks simply based on what she said?

Why is this so hard to accept? Anyway, it's besides the topic and a rather tiresome semantic back-and-forth at that.

I'm just talking about the comment, nothing more. If you guys want to argue based on TDP or how they can stamp these things or whatever, that is beyond me. I'm merely saying that the sentence that is so important to half of you can actually suggest more than you seem to want it to suggest.

 

[.vodka]

https://twitter.com/CPCHardware/status/814517066157977604

crappy google translate'd

Tomorrow we'll get clarification on the 5GHz string and more. Posting this on Reddit sure gave it the spotlight!

 

[KTE]

3.4Ghz base is already superior to INTEL's... Even higher? You want some user here and there to commit suicide?

Keller said that Zen has the same DNA of bulldozer (and Jaguar), for me, since the best of BD was the high clock, this means only that Zen has low FO4 as bulldozer, because there are not other good thing in bulldozer...

FO4 is not related to IPC. If they appear to be correlated, it's only because of existing designs. But there is not any reason to forbid low FO4 and high IPC designs...

Remember AMD statement of same energy/cycle as XV (namely same clock at same power). FX8370E, that is worse than XV in efficiency, reached 3.3/4.3 at 95W. Base clock was already promised >=3.4GHz... So I bet that we can hope of turbo max (1 core) of at least 4.4Ghz. Plus the auto OC feature that will push clock further...

Actually it was the NEON FPU of an ARM A53(?), 330mW of which 18 leakage and the other is dynamic.
It is a 2x64bit FPU. I estimated that the Zen FPU (4x128bit), implemented with the same FO4 (high, since is a synthetized ASIC) would draw about 1.2W and so a full CPU under 5W and so 32 zen core would be feasible at least at 2.41GHz in 180W... I posted also a graph of power/frequency scaling for that NEON FPU in which the power only tripled at 4.3GHz, respect to 2.41GHz. So under 15W/core at 4.3Ghz could be feasible. But this is an excess estimation, because a CPU does not draw 4x the power of the FPU and probabily Zen FO4 is not 30+ but way less....

EDIT: and the comparison you made is also more impressive, because the NEON FPU has 30+FO4, while we know that intel CPUs have about 26-28 FO4...

FO4 can be independent of IPC. Usually high IPC architecture have high FO4, but it is not automatic.

I already explained that but in synthesis:
Make the best architecture you can, with high IPC and high FO4. Split the stages until you reach the desired FO4. Then you have increased the stages and the branch misprediction penality, but usually the branch predictor has high success ratio. For blender, for instance, the branches were 7% of the instructions and the branch misprediciton was under 2%. Even if you double the stages, you double the penality on 2% of 7% of instruction. So you lose IPC, but of a negligible quantity. You increase the power at same Vcore, because you need more transistors, but you need less vcore for same frequency. In the end you can increase the frequency, to have same power you should lower the vcore, and so if you double the stages, you can't double the frequency, for power constraints and only losing a few % IPC.

Frequency was not ever process alone. There is also FO4. Not only at 32nm. At 90nm there was Pentium 4 speed daemon. At 65nm other P4 version and if i remember well yonah or merom, that were high fo4 low power and low clock...

Broadwell and Haswell should have same architecture and so same relative FO4. Absolute FO4 is different, because the process is different. I don't know max OC but i think that from 22FF to 14FF there was little gain. Most of the gain was from 32 bulk to 22 ff...



What can have taken from Bulldozer if not the low FO4? The low IPC? I don't think. He clearly stated that he took the speed from bulldozer. The one way is to have the same or better FO4.



Fo4 is what counts at same process...

I don't get it. 28nm BULK allow 4 base and 4.3 turbo and 4.9 overclock.
14nm is way better than 28nm bulk.
Now we must only know the FO4.
Hint: Keller speech. ... stating they have put bulldozer DNA in Zen. This can only mean the FO4 and a long pipeline. It was even simplified! (6x1way scheduler vs 1x4 way scheduler)
With low FO4 and better process, Zen should reach higher frequencies than excavator...

Where i am saying that it will have 5GHz@95W? FX9xxx have 220W TDP and clocks at 4.7/5GHz max. It's a 316mm2 chip. We can't have 220W on a <200mm2 chip, because it would melt. David Kanter on Real World Tech stated in a post that he never seen a chip with more than 1W per mm2 of TDP. I am not saying than you will have 95W@5GHz, but if a 316mm2 chip walls at 5.2GHz of OC, then another chip of 200mm2 walls at 5GHz, probabily the power consumed is not the same of the 316mm2 chip, because the area is smaller... So at same clock we have a chip that consumes less power... So probabily it will clock higher than the corresponding 8c@95W that was the FX8370E, rated at 3.3/4.3GHz... We all already know that the Zen base clock will be at least 3.4Ghz, so my statement is even backed up by official AMD statements. The only unknown is the turbo clock, but since at 5GHz draws less, probabily it will go higher than 4.3...

Stating that mine was faith ridiculize all my reasoning. I spent many time writing my reasoning and condensing all in the word faith, being an atheist, find this hylarious.
I have faith in my reasoning based on facts.
Stating that 5Ghz OC is ridicolous, without proof, is ridicolous...

Arghhh this is just in 2 pages! Same incessant words, over and over and over and over again. These parroted posts of yours form like 50% of this thread. If you keep going, Anand will need to sell all his remaining hair to fund bigger storage... What is the point of your endless repeat mode?

We get it, you love AMD and you love them to have 4.5GHz 8C 95W BDe IPC launch and improve to 5GHz soon trampling Intels best by 30%...

Everything about your posts and the posting style is reminding me of extreme fanatics, pardon my expression. You sound just like this guy: http://semiaccurate.com/forums/showpost.php?p=278509&postcount=4807


Insulting other members is not allowed
Markfw
Anandtech Moderator

(Opinions are own)

 

[ecogen]

https://twitter.com/CPCHardware/status/814517066157977604

crappy google translate'd

Tomorrow we'll get clarification on the 5GHz string and more. Posting this on Reddit sure gave it the spotlight!

Awesome, hopefully we can get something concrete.

 

[SlowSpyder]

I remember when Newegg and other sites promoted the FX9590 as "5GHz" because it could turbo there. I've been through enough of these launches to know I wouldn't count on anything just yet. We'll know soon.

 

[Abwx]

Ioff is what GloFo/Samsung referred to in figures.

Its the lower voltage due to lower Ioff leakage thats a by-product enabling lower power.

It says right there from the horses mouth.

Sent from HTC 10
(Opinions are own)

The horse is saying two things and you are focusing on the meaningless one..

Most of the power efficency improvement comes from the device better speed, aka better transconductance.
FI at 0.3W dynamic power there will be 90mW added leakage for 28nm SLP and 18mW leakage for 14nm LPP.

In comparison the improvement due to higher speed is almost 3x, that is, at 300mW dynamic power a A57 will clock at 2.4GHz with 14nm and 1.4GHz with low power 28nm SLP.

Wich also mean that at 1.4GHz 14nm LPP will use only 100mW dynamic power, as you can see lower Ioff, although noticeable, is a second order parameter in the whole improvement.

... What is the point of your endless repeat mode?

I guess that he can repeat the same things ad nauseam, even if they are substancied they wont enter in some brains that hang by here, so he s not exactly the one who is to blame for his own posts redundancies, indeed you have an exemple with my explanation about Ioff impact, several posts were necessary to explain the obvious...

 

[Dresdenboy]

Pentiun 4 had the right FO4 (13) to have max performance, but too low IPC: too few pipelines, no L1I cache relying on uop cache, too few decoders, and conceived for 32 bits and not 64 bits... A disaster... Then they switched to Yonah/Merom to be safe and not start over, that would have required much time...

Being a consumer CPU with area and power constraints they likely had to cut the design a bit. I wonder what the Tejas IPC looks like, although it is said, that IPC would be lower (but just derived from a longer pipeline).

No don't worry, they will just throw away any chip that runs slower(even 3.35 ones) because they have so much money that they just don't care...
Of course they will be binning their chips and release cheaper models at lower clocks,why on earth shouldn't they?

While I agree with you on the meaning of 3.4(+)GHz not being a lower limit, AMD might also bin slower dies for the Naples MCMs. Fab economics will naturally provide a wide distribution of clocks for a given power cap.

What make you think that the 3.4GHz was the top binning and not the low binning? They should only show a CPU that battled with a default 6900K, so a 3.4GHz sample would suffice. They hid also the max turbo, why don't hide also top bin frequency?...

See my answer above. I think, there will be one or more Ryzen models with a base clock of at least 3.4GHz, but not necessarily no cheaper models with base clocks below this mark. I think TheELF meant future products' clock distribution, while you are analyzing the demo'ed frequency.

 

[Doom2pro]

I have to ask, why are you so invested in FO4?

I know he gets really enthusiastic about FO4 but his arguments are valid as far as I can tell... He's just really invested in that particular area, and I don't know about you but I'd rather hear about gate latency from bjt2 than endless talk about Intel->AMD IPC conversion calculations (ugh). Or would you rather have that "Juan" particular guy in here going on and on about how his projections are always right (even when they aren't) and how x86 is doomed and how Zen is going to be a disaster (just because)?

Thankfully we don't have to deal with that character here, as far as bjt2 he brings much welcomed insight into the conversation, albeit repetitive at times I'll give you that.

 

[BeepBeep2]

While I agree with you on the meaning of 3.4(+)GHz not being a lower limit, AMD might also bin slower dies for the Naples MCMs. Fab economics will naturally provide a wide distribution of clocks for a given power cap..

But is that possible? Naples dies destined for an MCM package would possibly have different metal layers?

 

[Rifter]

I'll just say this.

Zen being a hit is good for everyone, why the intel fanboi's are getting there panties in a bunch really defies all logic, perhaps viral marketing truly is making a combeack and its going to be like the rollo days all over again. Or the poster saying they are really intel investors is bang on, cause then it does make sense.

That said we have seen absolutely nothing proving anything about IPC, sure this is a credible source and it very well may be legit, but until the NDA is up we cant trust anyone, thats the simple truth. I want to believe this as much as anyone but we still have a few weeks to go. All we have officially is the demo from last week that didnt show much really.

Also some mobo manufacturer better be planning on making a mobo with beefy VRM's i want to see what these bad boys can do at launch! I think hitting 5Ghz on air prime stable is a pipe dream but a guy can hope.