ZEN ES Benchmark from french hardware Magazine

[krumme]

Just lost my respect to Canard, if that was really included by the authors themselves and wasn't added by someone who prepared the magazine for printing.

Why is that?
And btw we hardly need Occam Razor to know this wasnt added by someone who prepared the magazine for printing.
They run their sample at the freq they have. Who knows where the 5GHz info is from. Perhaps their oem or their own sample. It really doesnt matter imo. They put their own name at risk here and they have been there practically since mechanical computers. So they are 100% sure.

 

[krumme]

Zen at 5ghz sounds ridiculous for one reason: AMD would be better than Intel. We can't absorb this kind of shock. Also, why are people saying this because of some flaky ENCODED magazine page?
I swear though, if AMD is trolling everyone with their 3.4ghz talk and then suddenly a huge OC bomb drops in all the reviews on release day, I will seriously laugh my ass off and then promptly buy a Zen platform.

Remember its an oc and we dont know if its all core or at what tdp.
Amd said 3.4 or higher for base. And thats for a 8c 95tdp model.
In that strict context its not that crazy but fairly straightforward.
But yeaa it is mentally crazy...
And btw this string is confirmed on the print

 

[krumme]

Its says a lot about the headroom.
Fottemberg teased great ST perf 6 days ago:
https://mobile.twitter.com/BitsAndChipsEng/status/812053325172580352

 

[bjt2]

Zen at 5ghz sounds ridiculous for one reason: AMD would be better than Intel. We can't absorb this kind of shock. Also, why are people saying this because of some flaky ENCODED magazine page?
I swear though, if AMD is trolling everyone with their 3.4ghz talk and then suddenly a huge OC bomb drops in all the reviews on release day, I will seriously laugh my ass off and then promptly buy a Zen platform.

Keller said this 2 years ago: https://www.youtube.com/watch?v=idRLZTy9Pio&feature=youtu.be&t=5m1s

Zen was thought from the beginning as speed daemon as bulldozer (low FO4) and low power as Jaguar...

 

[Dresdenboy]

Just lost my respect to Canard, if that was really included by the authors themselves and wasn't added by someone who prepared the magazine for printing.

As it is in a different, but still processor related article, it might have been included by the authors/editors.

 

[KTE]

Its says a lot about the headroom.
Fottemberg teased great ST perf 6 days ago:
https://mobile.twitter.com/BitsAndChipsEng/status/812053325172580352

Hmm... Not sure I trust any of these sources...

Sent from HTC 10
(Opinions are own)

 

[cytg111]

Zen at 5ghz sounds ridiculous for one reason: AMD would be better than Intel. We can't absorb this kind of shock. Also, why are people saying this because of some flaky ENCODED magazine page?
I swear though, if AMD is trolling everyone with their 3.4ghz talk and then suddenly a huge OC bomb drops in all the reviews on release day, I will seriously laugh my ass off and then promptly buy a Zen platform.

I've said it before, it sure looks like they're slowplaying this hand.

 

[Doom2pro]

I've said it before, it sure looks like they're slowplaying this hand.

Well considering they did the exact opposite with their last major design (Bulldozer) they kinda have to sandbag this one

 

[rvborgh]

i am going to laugh my rear end off if Zen ST beats Intels

https://mobile.twitter.com/BitsAndChipsEng/status/814184127339655169

 

[EXCellR8]

I already tore down my FX machine so I'll be grabbing a Zen regardless of how it performs in games compared to Sky/Kaby.

Now I just need the socket specs so I can figure out what water block doesn't exist yet...

 

[PhonakV30]

Fake , not possible at 5GHz,. mark my word.If they did , then It was 100% LN2

 

[moonbogg]

I've seen some fishy looking documentation showing the full Zen chip being priced at just under $600. Makes sense to me and sounds perfect. The locked version was just under $400. If I can get the same clocks as my current chip with a decent IPC increase, plus the extra 2 cores, plus the hilarity of actually having an AMD rig again, I will buy it guaranteed. Also, when Zen+ comes out, I can buy that too, maybe even Zen++ without having to buy a whole new BOARD like Intel forces us to do. SkylakeX will not compete because it will cost twice as much.
Its like asking people right now, "Would you rather have a 6900K for $600 or a Skylake 8 core for $1,100? I wonder what they'd pick.
See, I like what AMD is doing. They are releasing a consumer chip with some balls attached to it. None of this forcing people to buy a quad channel server board just to get more than 4 cores. Ridiculous. Intel ignored the desktop market for a decade by releasing the same quad core chip over and over. Now AMD will, as they have many times before, be the first to break the mold in this area and give us a chip with some weight behind it, on a consumer board and at a consumer price point.
Intel has two choices. Cut the price of their HEDT products in half or experience a massive stall in sales. I expect the latter.

 

[KTE]

If true, i will say hello... Now let's be cautious...

On another forum where I am more "respected" i put my true forecast, that was 4 base and 4.8-5 turbo for the 8c. If an A0 ES sample can really OC at 5GHz on air, maybe i am not so far...

So could Haswell...

Means nothing @ DT TDPs.

You were arguing 4.0-4.5GHz 8-Core 95W launch 4.5-5.0GHz Turbo at 1.23v minimum.

You kept saying BD/XV 1.43v can hit 4.9GHz at 28nm bulk hence.... Zen can do so much more, etc.

We've had a post here by someone before too:

And this post by mclarenfan1968 2 years ago:

Sent from HTC 10
(Opinions are own)

 

[EXCellR8]

Intel has two choices. Cut the price of their HEDT products in half or experience a massive stall in sales. I expect the latter.

I feel like consumer PC products count for a whopping 10% of Intel's sales though... they're products are in everything under the sun and if not, they profit from partnerships and massive data center installments.

 

[Thunder 57]

http://www.anandtech.com/show/2594/9

Thank you, that's exactly what I was looking for. Since it's in there as well, I thought the decision for an inclusive cache for Zen was interesting. What surprised me was the L3 not being inclusive (though not exclusive either, IIRC. I believe on previous AMD designs they referred to this as "non-inclusive" L3). The reason I figured they would go all inclusive was because of this:

The benefit is that if the CPU looks for data in L3 and doesn’t find it, it knows that the data doesn’t exist in any core’s L1 or L2 caches - thereby saving core snoop traffic, which not only improves performance but reduces power consumption as well.

The other consideration is that Intel only loses 256KB per core in the L3, whereas if AMD used an inclusive L3 it would lose 512KB per core. Any thoughts on this anyone?

 

[KTE]

I personally will get a Zen build up and running as fast as possible... I love new uarchs.

But I'll get to test one from work quicker than that as we are their biggest partner for decades...

AMD would seriously surprise me at higher than 3.5GHz base 95W 8Core.

Clocks... I expect 4.1-4.4GHz stable air OCs from launch products.

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(Opinions are own)

 

[KTE]

The other consideration is that Intel only loses 256KB per core in the L3, whereas if AMD used an inclusive L3 it would lose 512KB per core. Any thoughts on this anyone?

The whole cache lines are duplicated in the lower buffer if inclusive, yes.

L1 may well be 'inclusive' of the uop cache... As is normally done

I'm curious to know the uop cache eviction method being used for Zen.

Sent from HTC 10
(Opinions are own)

 

[itsmydamnation]

Hmm... Not sure I trust any of these sources...

Sent from HTC 10
(Opinions are own)

Yes you should totally trust FPiednoel when it comes to AMD because he would know right.

I have to go back to my default position of why not? There is nothing i can see that says Zen cant hit 5.0ghz on air. We know lots of performance comes from predictors/prefetch/uop cache and far better L2. None of those look clocking liming, they broke down the really latency sensitive area into 6 individual schedulers and we know what bulldozer could hit with a 4 wide scheduler. One big unknown is what the iPRF looks like but the fPRF in BD has a very larger amount of read and write ports and it doesn't limit clock.

So im not going to say Zen cant hit 5.0ghz on air but the people who are can you be specific as to why?

 

[USER8000]

What if the 5GHZ parts are super leaky ones which are rated at a higher TDP??

 

[KTE]

Yes you should totally trust FPiednoel when it comes to AMD because he would know right.

I have to go back to my default position of why not? There is nothing i can see that says Zen cant hit 5.0ghz on air. We know lots of performance comes from predictors/prefetch/uop cache and far better L2. None of those look clocking liming, they broke down the really latency sensitive area into 6 individual schedulers and we know what bulldozer could hit with a 4 wide scheduler. One big unknown is what the iPRF looks like but the fPRF in BD has a very larger amount of read and write ports and it doesn't limit clock.

So im not going to say Zen cant hit 5.0ghz on air but the people who are can you be specific as to why?

While I disagree with him on many fronts, he is a verified competing professional knowing a lot more about real world chip tech than most here.

His statements are no different to Lisa et al. Both biased, both ulterior motives, both PR.

BTW I didn't say it can't OC to xMHz. Ever.

I said it won't launch at those MHz at 95W (since the very start).

Sent from HTC 10
(Opinions are own)

 

[itsmydamnation]

BTW I didn't say it can't OC to xMHz. Ever.

I said it won't launch at those MHz at 95W (since the very start).

Sent from HTC 10
(Opinions are own)

I wasn't directing that at you or anything and no i dont think 5ghz in 95watt TDP is likely. But 8core BD-E hits pretty consistent 4.4 oc on air so 5ghz is 13% higher, we have the german Overclocker saying he has used Zen and that it beats BW-E but not enough to go replace a X99 system. Those data points align pretty well if we consider overall Approx the same IPC.

 

[Thunder 57]

The whole cache lines are duplicated in the lower buffer if inclusive, yes.

L1 may well be 'inclusive' of the uop cache... As is normally done

I'm curious to know the uop cache eviction method being used for Zen.

From what I remember L1 and L2 are inclusive. L3 is not, but not necessarily exclusive either. What I guess I was trying to say is for Intel at 256K L2, only 1MB is duplicated in L3 for a quad core, or 2MB for an octacore. The benefit of "losing" that 2MB is much less snooping. That saves you bandwidth, latency( I think), and power.

In Zen L2 is 512K, so with an inclusive L3 twice the data would be duplicated. For an 8 core zen, that would mean 4MB out of 8MB L3 would be L1/L2. So it appears AMD went for a faster L1/L2 whereas the preferred capacity in L3. This is just my opinion based on what I know, and I could be wrong.

What if the 5GHZ parts are super leaky ones which are rated at a higher TDP??

Sounds an awful lot like an FX-9590 .

 

[Abwx]

What if the 5GHZ parts are super leaky ones which are rated at a higher TDP??

Unlikely, leakage is 5x lower than with 28nm HPP, and due to the Finfets characteristics there is less variability in this respect.

That being said 14nm LPP is considerably faster than 28nm HPP, of course this is not a guarantee that max frequency will be significantly higher.

There s other paramaters at work that have a say but in the linear part of their curves 14nm LPP is 2x faster than said 28nm...

Remember the slide below.?.

The x axys is the time, and the y axys is the output level of a gate that is driven by a step function and whose output is loaded by one or several gates inputs.

Although the axys are not officialy referenced like this underlying mathematics say that it is also so.

This of course give an accurate idea of the FO4 delay improvement, explained ad nauseam by who you know, that is potentialy possible with 14nm.

 

[itsmydamnation]

From what I remember L1 and L2 are inclusive. L3 is not, but not necessarily exclusive either. What I guess I was trying to say is for Intel at 256K L2, only 1MB is duplicated in L3 for a quad core, or 2MB for an octacore. The benefit of "losing" that 2MB is much less snooping. That saves you bandwidth, latency( I think), and power.

In Zen L2 is 512K, so with an inclusive L3 twice the data would be duplicated. For an 8 core zen, that would mean 4MB out of 8MB L3 would be L1/L2. So it appears AMD went for a faster L1/L2 whereas the preferred capacity in L3. This is just my opinion based on what I know, and I could be wrong.



Sounds an awful lot like an FX-9590 .

for Zen the L3 holds the Tags for all data in the core L2's So you dont get the full 8mb per CCX as an eviction cache.
For Intel ring bus the L1 and L2 are inclusive in the L3 so its all cores L1+L2 but its not write through so the data in the L3 can be stale. https://en.wikipedia.org/wiki/MOESI_protocol

Its really about scalability the ring bus can scale to more cores then AMD's CCX solution but the price is latency. at the 4core count size i dont think either are better or worse, but im guessing the inter CCX latency going to be high and at that point the ring bus starts to be better but then it starts to run into issues and thats why intel have a new fabric for knights whatever they are upto.

 

[Thunder 57]

for Zen the L3 holds the Tags for all data in the core L2's So you dont get the full 8mb per CCX as an eviction cache.
For Intel ring bus the L1 and L2 are inclusive in the L3 so its all cores L1+L2 but its not write through so the data in the L3 can be stale. https://en.wikipedia.org/wiki/MOESI_protocol

Its really about scalability the ring bus can scale to more cores then AMD's CCX solution but the price is latency. at the 4core count size i dont think either are better or worse, but im guessing the inter CCX latency going to be high and at that point the ring bus starts to be better but then it starts to run into issues and thats why intel have a new fabric for knights whatever they are upto.

Great information. I remember reading about MESI years back but I haven't really kept up with cache coherency and multicore. So the L3 only holds the tags, and can act almost like a pointer to the valid data? Makes sense. Also they are all write back this time, where BD had a write through L1. I didn't understand why they did that. I didn't think there was much reason to use write through cache these days (simplicity?).

This leads me to a further question; Are both MOESI and MESIF two different ways of accomplishing the same thing?