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Discussion Zen 7 speculation thread

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Fjodor2001 said:
From previous discussions in this thread, the current assumption is that Zen7 will be 32C/64T for top SKU and 16C/32T per CCX on DT.

If that turns out to be the case, then what can be expected for the bottom SKU, e.g. 12C/24T? That would map to the current case for Zen5 where we have 8C/16T for a fully working CCX, and 6C/12T for bottom SKU which is 75% of the fully working one.
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There will also be 8C/16T CCD for low end.
 
Claudiovict said:
Ryzen 5 or they would bring back Ryzen 3? A Ryzen 5 with 6 cores in 2028(?) would be incredible mediocre
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To expand upon what @adroc_thurston said, that decision is made fairly late in the process as it directly impacts margins, revenue, and such. They will charge as much as possible for as little as possible. All of that will be determined based on the economy, competitors, etc. AMD is the market leader when it comes to mainstream, high performance CPUs, so expect to have to pay more for less, rather than less for more.

Great to see the forums back up. 🍻
 
eek2121 said:
To expand upon what @adroc_thurston said, that decision is made fairly late in the process as it directly impacts margins, revenue, and such. They will charge as much as possible for as little as possible. All of that will be determined based on the economy, competitors, etc. AMD is the market leader when it comes to mainstream, high performance CPUs, so expect to have to pay more for less, rather than less for more.

Great to see the forums back up. 🍻
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Yeah, but if they have 16C/32T CCD as base, how many of those will have so few working cores that it’s worth binning into 6C/12T?

And then onwards into 8C, 10C, 12C, 14C? And that’s only for SKUs based on single CCD. Then there will be further SKUs based on 2xCCD going onwards, so … 28C, 30C, 32C?

How many Zen7 SKUs do you expect them to have on DT?
 
Fjodor2001 said:
From previous discussions in this thread, the current assumption is that Zen7 will be 32C/64T for top SKU and 16C/32T per CCD on DT.

If that turns out to be the case, then what can be expected for the bottom SKU, e.g. 12C/24T? That would map to the current case for Zen5 where we have 8C/16T for a fully working CCD, and 6C/12T for bottom SKU which is 75% of the fully working one.
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Doesn't seem likely. I doubt AMD would design a 12C CCD just to abandon it after one generation.

Fjodor2001 said:
Yeah, but if they have 16C/32T CCD as base, how many of those will have so few working cores that it’s worth binning into 6C/12T?

And then onwards into 8C, 10C, 12C, 14C? And that’s only for SKUs based on single CCD. Then there will be further SKUs based on 2xCCD going onwards, so … 28C, 30C, 32C?

How many Zen7 SKUs do you expect them to have on DT?
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Cores don't have to be bad to disable them. It would be wasteful though hence I don't think we'll see a 16C CCD with Zen 7. Even if we did, I would expect the low core offerings to be mobile based just like I expect anything 6C or less from Zen 6. I don't see AMD disabling half the cores for a 6C desktop part. An 8C part could be done with garbage silicon like the 5600 non X and below were that can't meet frequency/power requirements.
 
Fjodor2001 said:
From where did you get that info?
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MLID showed 8 core chiplets that can be added to Zen 7 Halo. So, if these chiplets exist, then they would also be used in low end desktop.

BTW, this strategy of AMD of having "Halo" product and not pairing them with V-Cache chiplet is a head scratcher and an opportunity lost.

1765433982742.png
 
eek2121 said:
Great to see the forums back up. 🍻
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Yeah that was bad. Sorry for off-topic but in case my sig isn't enough, everyone please consider registering on forums.thefpsreview.com and/or anfy.ca in case of future interruptions which may or may not be permanent. Hopefully that will never come to pass, but it pays to be prepared, and having another forum to post on isn't necessarily a bad thing.

Sorry for the interruption.
 
Joe NYC said:
BTW, this strategy of AMD of having "Halo" product and not pairing them with V-Cache chiplet is a head scratcher and an opportunity lost.
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Same reason they have taken forever to finally push out a 2x X3D SKU.

It's expense on top of expense.

The packaging required for Halo chiplets is IIRC more cost intensive compared to the "xyz Range" desktop CPU SKUs.

When you add that to X3D packaging costs as well it's a lot.
 
soresu said:
Same reason they have taken forever to finally push out a 2x X3D SKU.

It's expense on top of expense.

The packaging required for Halo chiplets is IIRC more cost intensive compared to the "xyz Range" desktop CPU SKUs.

When you add that to X3D packaging costs as well it's a lot.
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I imagine that the Zen 6 CCD with V-Cache and without V-Cache will have the same pinout (or layout of the bumps) and they can be interchangeably added.

Problem in Strict Halo is that they don't already have the CCD for Srix Halo (which is unique) that also has V-Cache.

So it seems like problem solved in Zen 6, and then broken again in Zen 7.
 
DrMrLordX said:
Yeah that was bad. Sorry for off-topic but in case my sig isn't enough, everyone please consider registering on forums.thefpsreview.com and/or anfy.ca in case of future interruptions which may or may not be permanent. Hopefully that will never come to pass, but it pays to be prepared, and having another forum to post on isn't necessarily a bad thing.

Sorry for the interruption.
Click to expand...
Sigs don’t show up on the mobile site, just an fyi.
 
Joe NYC said:
MLID showed 8 core chiplets that can be added to Zen 7 Halo. So, if these chiplets exist, then they would also be used in low end desktop.

BTW, this strategy of AMD of having "Halo" product and not pairing them with V-Cache chiplet is a head scratcher and an opportunity lost.

View attachment 134974
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Also from that slide:

1765561333215.png
Which says: "No support for 2-Hi V-Cache. This further suggests that AMD won't "double stack" V-Cache slices on client until Zen 8 at the earliest"

At the same time we have this however:

wccftech.com

AMD Ryzen 9 9950X3D2 & Ryzen 7 9850X3D CPUs - Here's Everything We Know About The 'Soft Refresh' of Zen 5 3D V-Cache Series

AMD is preparing to launch new Zen 5 X3D CPUs, the Ryzen 9 9950X3D2 & Ryzen 7 9800X3D, which carry on the legacy built by the 9000X3D family.
wccftech.com wccftech.com

Suggesting 9950X3D2 will have "192 MB of Cache (Dual X3D CCDs)".

So what to make of that? We'll get 192 MB V-Cache already with Zen5 Refresh SKUs that have 2x CCD, but not 192 MB (or 2x whatever the relevant V-Cache slice will contain) per single CCD until Zen8?
 
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