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Discussion Zen 7 speculation thread

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dangerman1337 said:
IMEC Has A7 node being the first gen of CFET which is due about 2031 (probably 2032 realistically) and subsequently A5 in 2033 (again 2034 most likely).
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Hold on a second here IMEC Roadmap is not practical for commercialization . It says N2 2024 and A14 2026 we are gretting N2 in 2025-6 and A14 2028-9H3YgU2WqwLUH59BXUYVZd9-1755164337.png
 
511 said:
Hold on a second here IMEC Roadmap is not practical for commercialization . It says N2 2024 and A14 2026 we are gretting N2 in 2025-6 and A14 2028-9View attachment 128779
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They have a more recent one:

Figure%201%20-%20Imec%20roadmap.png


So yeah A7 being HVM hopefully in 2032 is plausible.
 
dangerman1337 said:
So yeah A7 being HVM hopefully in 2032 is plausible.
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Meh, I think we have to accept we're probably moving to three year cycles. With nodes getting more expensive more and more customers are going to want to amortize their design/mask costs for longer periods, and the gains of a "major node" continue to shrink. So instead of major node at time+0y, followed by a 'P' version at time+1y, followed by the next major node at time+2y, we'll start to see two 'P' type nodes before the next major node.

This is arguably already the case and we just haven't acknowledged it yet. Apple is doing its third iPhone with an N3 family node, and N2 ships in volume in 2026 and all indications are that A14 won't ship in volume until 2029.

IMEC doesn't exactly have a good track record with their roadmaps. Still waiting on 450mm wafers lol
 
igor_kavinski said:
How has it radically changed since 2020?
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two from the top of my head:

laptop = desktop

mobile phone upgrades = meaningless


basically chips got extrmly performant at 0-100w and everything extra is mostly score

0-50w chips run everything sufficiently, cool, fast, no lag

etc. big thermal/w optimization era
 
But there's nothing radical that's happened. No new paradigm shift. CPUs haven't learned any new tricks.

No SMT4, for example.

6 GHz was breached but not for mainstream CPUs. That should obviously change in 2026. Maybe 8 GHz by 2030 if we are very lucky?

APX looks great on paper and hoping it debuts in Zen 7 at least.

I think the next radical shift in computing will be when a single thread's multiple branches can be processed in parallel on different cores and instead of flushing the pipeline on the wrong branch prediction, the context simply changes to the core processing the correct branch.
 
igor_kavinski said:
But there's nothing radical that's happened. No new paradigm shift. CPUs haven't learned any new tricks.
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Well, uh, yeah.
Normal ass cores won eons ago when speed daemons died an untimely death at the hands of Dennard Scaling.
igor_kavinski said:
No SMT4, for example
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POWER has it and Vulcan and derivatives (Triton) had it too. But it's not worth much.
igor_kavinski said:
6 GHz was breached but not for mainstream CPUs. That should obviously change in 2026. Maybe 8 GHz by 2030 if we are very lucky
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Means to an end.
igor_kavinski said:
APX looks great on paper
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It doesn't.
It's aa64 thingies while missing the very point of why aa64 exists (cleaning up the ISA).
igor_kavinski said:
I think the next radical shift in computing will be when a single thread's multiple branches can be processed in parallel on different cores and instead of flushing the pipeline on the wrong branch prediction, the context simply changes to the core processing the correct branch
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I just love extending the sidechannel attack surface even further beyond.
What could possibly go wrong?
 
adroc_thurston said:
I just love extending the sidechannel attack surface even further beyond.
What could possibly go wrong?
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Put the responsibility on the user.

If the user is not sure if some malicious process is running on the CPU, then don't use the feature.

Spectre/Meltdown was much ado about nothing. Is there a single widespread instance of operating systems running on unpatched CPUs getting compromised?
 
I was wondering, if Zen 7 is on A14 in 2028... could there be a Zen 7+ on A14 SPR in 2029 per TSMC's roadmap? I feel if Zen 8 is 2030 and with TTL & HML in 2028 & 2029 that AMD will probably will want to have something to compete against those two.
 
dangerman1337 said:
I was wondering, if Zen 7 is on A14 in 2028... could there be a Zen 7+ on A14 SPR in 2029 per TSMC's roadmap? I feel if Zen 8 is 2030 and with TTL & HML in 2028 & 2029 that AMD will probably will want to have something to compete against those two.
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If it's on A14 there will be no Zen 7 in 2028 it will be in 29 and we would have DDR6 by than
 
511 said:
If it's on A14 there will be no Zen 7 in 2028 it will be in 29 and we would have DDR6 by than
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Maybe but I don't think even Zen 7+ on A14 SPR would necessarily justify DDR6 in 2029. Like DDR5 is going to get faster (already at 8400 MT/s CUDIMM, imagine what CAMM2 DDR5 will bring) between now and the next few years and AMD will probably want something to go against TTL & HML as an interim.

I mean Zen 8 will be 100% DDR6 for sure, just a question if AMD can release it with 1nm CCDs maybe late 2029 somehow or it has to be 2030, or Zen 8 is A14 SPR.
 
511 said:
that's just impossible ain't no way we get 10A in 2029 even 30 is best case
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Yeah true, I mean if RZL is a Zen 7 competitor then where does that leave AMD Vs TTL & HML? I suppose TTL won't offer much improvement ST wise over RZL (probably focused on MT more so, but having Unified Core on par with Griffin Cove ST wise) but then we reach HML and if Zen 8 is on 1nm end of 2030 say then that's a huge gap AMD needs to fill in. A14 SPR Zen 7+ would fit neatly in 2029.
 
computing is already super powerful........

AI will soon be able to heavily optimize software and enable huge performance gains

it's not too far it will be able to rewrite whole parts in assembly or similar

optimized software + zen 6 era will make everything run like a breeze

who will need zen 7 other than datacenters?
 
igor_kavinski said:
I think the next radical shift in computing will be when a single thread's multiple branches can be processed in parallel on different cores and instead of flushing the pipeline on the wrong branch prediction, the context simply changes to the core processing the correct branch.
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This very simple form of speculative execution won't be implemented¹, because it would be a huge waste of energy: Most of the time the CPU would be doing work which will be discarded. Besides energy consumption, the added stress on the memory subsystem would be a problem too.

________
¹) In general computing at least; maybe there are niche applications of such an approach.
 
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