Discussion Zen 7 speculation thread

[BorisTheBlade82]

I would say NVidia too. They would like to put a big number on their dGPUs and later iGPU tiles.

Congratulations, hereby you've been awarded the title "Captain Obvious of the Day" 😉
And shame on @igor_kavinski for not using the mandatory <sarcasm> tags.

 

[igor_kavinski]

And shame on @igor_kavinski for not using the mandatory <sarcasm> tags.

So little faith in Intel

 

[Joe NYC]

So little faith in Intel

Can Qualcomm get a participation trophy?

 

[511]

Can Qualcomm get a participation trophy?

does their GPUs even have GEMM

 

[MrMPFR]

Edit: Forgot this is the Zen 7 thread, so would this be feasible at all for a CPU architecture? Maybe AMD processing in-cache 3D V-Cache for zen7 xD
Edit 2: moved to appropriate thread, link: https://forums.anandtech.com/threads/rdna-5-udna-cdna-next-speculation.2624468/post-41515323

 

[marees]

So it seems, but patent specifies it can be any non-local cache, so they could be coupled to Shader Engine private cache, L2, or MALL.
If the reduced L2 (AT2 = 24MB L2 vs Navi 48 = 64MB MALL) is accurate and CCU is leveraged for RDNA 5 then those being coupled to L2 would shrink L2 for other processes since they require sizeable dedicated. Wonder how AMD engineers would tackle this. A SE cache implementation could happen as well, but it would require a much bigger SE cache, but some other benefits like superior cache latency, closer integration with CUs (routing and latency) etc... Latter seems more likely given the entire thing about the supposedly (not confirmed IIRC) overhaul with autonomous SE scheduling and dispatch (WGS and ADC). In this case CCUs outside SEs would complicate things alot.

Remember CCU offloads work from CU, so overhead might be lower than what it seems. No need to duplicate instructions, but yeah still some overhead, but how much?

Highly doubt that. But some BW heavy RT instructions could be offloaded to CCUs.

Again lots of unaswered questions but one of the most interesting AMD patents in a long time and a massive departure architecturally from anything previous.

Edit: Forgot this is Zen 7 thread, so would this be feasible at all for a CPU architecture? Maybe AMD processing in-cache 3D V-Cache for zen7 xD

We have a RDNA 5 thread

 

[marees]

Forgot this is Zen 7 thread, so would this be feasible at all for a CPU architecture? Maybe AMD processing in-cache 3D V-Cache for zen7 xD

AVX 512 implementations maybe ??

 

[adroc_thurston]

so they could be coupled to Shader Engine private cache

no such thing, they hacked out the L1 outta hierarchy with RDNA4.

Wonder how AMD engineers would tackle this.

By making it a CPU.