Zen6 could enable both decoder clusters for ST mode, thus enabling 8-instruction decoding beyond SMT mode.
This is entirely feasible.
I also think that L1-I of at least 48KB 12-Way is also quite feasible in Zen6. From what I understand, the 32KB L1-I capacity is a bigger limitation for the Zen5 than the same ITLB as the Zen4. However, I suspect the ITLB will also be larger in the Zen6.
Whether this will happen depends on AMD's priorities and goals.
Edit:
Judging by the redesigned ALU scheduler, it's unlikely AMD will be able to count on subtle changes and improvements, as Intel is constantly in flux. AMD needs to make bold and consistent changes and improvements in this race. Zen5 was just a starting point.
I could be wrong, but I have a feeling Zen6 will be a solid generation.