Question Zen 6 Speculation Thread

[adroc_thurston]

... any other way than adroc doesn't believe AVX10 supports 128b or 256b (which it clearly does). Of course he COULD clarify his difficult to justify statement to explain himself.

You're mandated to support 512b across every AVX10 implementation.
xmm/ymm modes are a part of the baseline AVX512 since 2017.

 

[Covfefe]

Thanks.

From your linked document:


From your link:

As much as I respect this source, this is speculation ..... and I seriously doubt it.

I believe that future e-cores will support AVX10 with a 128 bit path and that P cores will likely support a full 512 bit path. This is my speculation.; however, the SPEC linked by @511 clearly shows that it supports 3 different bit paths .... not ONLY 512bit.

Also, his statement is incomplete. "AVX10 had intended to allow 256 or 512 bit modes depending upon processor capabilities". He left off 128bit further raising doubt to the speculation statement.

And I don't know how you interpret adroc's statement:


... any other way than adroc doesn't believe AVX10 supports 128b or 256b (which it clearly does). Of course he COULD clarify his difficult to justify statement to explain himself.

128-bit-only mode was already killed a couple years ago.

FCLC (@fclc@mast.hpc.social)

LETS GOOOOO #Intel listened! No more ambiguity, no more questioning, 128 bit only implementations are no longer valid for #AVX10! A massive thanks to the Intel ISA folks! And a major thanks to @chipsandcheese@techhub.social for giving me a platform to express my concerns on the spec! For...

mast.hpc.social

 

[511]

Thanks.

From your linked document:


From your link:

As much as I respect this source, this is speculation ..... and I seriously doubt it.

I believe that future e-cores will support AVX10 with a 128 bit path and that P cores will likely support a full 512 bit path. This is my speculation.; however, the SPEC linked by @511 clearly shows that it supports 3 different bit paths .... not ONLY 512bit.

That's not true so initially there were three implementation of vector length 128/256/512b 128 got killed and so did 256bit vector linked in phoronix article now we only got 512 vector length . I mean the size supported by HW.

And than there is the size of data you can have 128/256/512b vectors with respective instructions which is different from hardware Maz supported vector length.

 

[OneEng2]

It's my understanding that AVX10 is designed to provide a single code base the ability to run on a variety of cores having various levels of bit widths in the execution path.

AMD are certainly not going to need to support anything other than 512b.

Intel p cores ? Likely 512b.

Intel e cores? I'm guessing 128b and maybe 256b.

What is the point of AVX10 over AVX512 if not for the variable bit widths?

 

[adroc_thurston]

It's my understanding that AVX10 is designed to provide a single code base the ability to run on a variety of cores having various levels of bit widths in the execution path.

No. It's 512b only. The underlying FMA hardware can be smaller, but regs/shuffle etc no luck.

What is the point of AVX10 over AVX512 if not for the variable bit widths?

It was the point.
Then AMD showed the rightful way.