Question Zen 6 Speculation Thread

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Doug S

Diamond Member
Feb 8, 2020
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N2X will allow +10% fmax over N2 according to TSMCs own slides.

14% is not a nothingburger, its actually a pretty big burger when you consider the largest gen on gen freq increase Ryzen has ever achieved was 16%, and that was only achieved once in 6 generations-- in 5950X to 7950X. The next biggest uplift, going from 12nm to 7nm, only got them 9% on paper (4.7 3950X vs 4.3 2700X). That uplift was even less in practice than on paper. That also completely ignores that the physical challenges of switching transistors at a much higher absolute frequency, at the high end of C band approaching X band.

Yep and I invite people to look at Apple's frequency gains over the same timeline as Ryzen. They got MUCH more only because they were starting from a far lower frequency and - importantly - far lower power.

Newer processes don't promise 10% "fmax", they promise 10% faster transistor switching time. That is not the same thing, a lot of what would be transistor switching gains translating into frequency gains is eaten by stuff unrelated to transistor switching time such as synchronization delays and those only increase as CPUs get more complex. Also the promises of a new node "x% faster at same power or y% less power" stuff assumes the SAME design, with the same number of transistors. That's not an assumption valid in the real world, because there are always more transistors. If you get a 10% shrink and increase your transistor count by ~10% as a result that means a ~10% gain in power, so unless you want to increase your TDP by that same ~10% you must take less than x% faster switching speed.

Because Apple has been coming from a lower power world they've had more room to accept TDP increases. They've had reason to since their cores are now used in PCs instead of only phones. They've moderated that hit somewhat via the lower frequencies in phones but it is still showing up with higher TDPs in their iPhone SoCs ever since the A14 generation which was when M1 appeared. By contrast, AMD/Intel have been bumping up against reasonable TDP limits for quite a while, so they have less room to increase their TDP by the same percentage as the increase in transistor count. Apple will eventually bump up against the same limits and be restricted to the same frequency gains as AMD/Intel - they'll settle at a lower frequency range than AMD/Intel because despite their TDP increases they still place a much higher value on efficiency than the x86 world.
 

adroc_thurston

Diamond Member
Jul 2, 2023
7,660
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Yep and I invite people to look at Apple's frequency gains over the same timeline as Ryzen. They got MUCH more only because they were starting from a far lower frequency and - importantly - far lower power.

Newer processes don't promise 10% "fmax", they promise 10% faster transistor switching time. That is not the same thing, a lot of what would be transistor switching gains translating into frequency gains is eaten by stuff unrelated to transistor switching time such as synchronization delays and those only increase as CPUs get more complex. Also the promises of a new node "x% faster at same power or y% less power" stuff assumes the SAME design, with the same number of transistors. That's not an assumption valid in the real world, because there are always more transistors. If you get a 10% shrink and increase your transistor count by ~10% as a result that means a ~10% gain in power, so unless you want to increase your TDP by that same ~10% you must take less than x% faster switching speed.

Because Apple has been coming from a lower power world they've had more room to accept TDP increases. They've had reason to since their cores are now used in PCs instead of only phones. They've moderated that hit somewhat via the lower frequencies in phones but it is still showing up with higher TDPs in their iPhone SoCs ever since the A14 generation which was when M1 appeared. By contrast, AMD/Intel have been bumping up against reasonable TDP limits for quite a while, so they have less room to increase their TDP by the same percentage as the increase in transistor count. Apple will eventually bump up against the same limits and be restricted to the same frequency gains as AMD/Intel - they'll settle at a lower frequency range than AMD/Intel because despite their TDP increases they still place a much higher value on efficiency than the x86 world.
Mucho texto.
QC got 19% off a single shrink with a tiny bit of Vmax cranking.

Speed is nice. Speed is normal.
 

poke01

Diamond Member
Mar 8, 2022
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QC got 19% off a single shrink with a tiny bit of Vmax cranking.
Qualcomm cores cranking up doesn’t seem impressive to me.

Their standard X2 Elite N3P core clocks up to 4.7GHz. The M5 does 4.6GHz but it’s wider and more fat AND more efficient/faster than QCs.

yes it’s small but that’s the only thing going for qc. So to do well in benchmarks they needed to use N3X.
 

adroc_thurston

Diamond Member
Jul 2, 2023
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Qualcomm cores cranking up doesn’t seem impressive to me.
It's still a huge core going 5G at 2.2mm^2 on N3x. Good.
Their standard X2 Elite N3P core clocks up to 4.7GHz. The M5 does 4.6GHz but it’s wider and more fat AND more efficient/faster than QCs.
I'm not sure M5 is actually more efficient than non-5G Pegasus parts.
yes it’s small but that’s the only thing going for qc. So to do well in benchmarks they needed to use N3X.
It's good.
It's speedy and fast and stuff and going fast is nice.
Pump in the juice.
 

poke01

Diamond Member
Mar 8, 2022
4,511
5,821
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Not nT. LITTLEs carry Apple there.
I mean general 1t efficiency in GB6/sir2017 1 copy etc etc.
i mean ST.
4.6GHz V3 is slower vs a 4.2GHz A19 P core. This is the best picture I can give you. But we will know more whenever QC launches X2 elite next year.

IMG_2964.png
 

adroc_thurston

Diamond Member
Jul 2, 2023
7,660
10,414
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Why do you think that? There are a lot of unknowns about how it will perform (since no prior model with bLLC exists), so is there any reason to believe that NVL-S bLLC will perform either better or worse than Zen6 X3D?
Intel L3 sucks donkeyballs.
More donkeyballs L3 is not a magic bullet, especially for cores as generally cache-rich as coves.

Current LNC in ARL-S has 3 times the L2 capacity and an additional L1.5 dcache to have tied gaming perf with non-V$ Zen5.
 

Fjodor2001

Diamond Member
Feb 6, 2010
4,296
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Maybe they need to redesign their core design and they don’t want to till unified core
Or they don’t need to redesign it for bLLC to work as intended. Otherwise why not wait with introducing bLLC until unified core is released.

Or the redesign they’ll make with NVL-S will be sufficient.
 

DrMrLordX

Lifer
Apr 27, 2000
23,042
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Why do you think that? There are a lot of unknowns about how it will perform (since no prior model with bLLC exists), so is there any reason to believe that NVL-S bLLC will perform either better or worse than Zen6 X3D?
While others seem to have addressed this question rather well, it seems that (for now) Intel hasn't progressed much IPC-wise with thier P cores over the last few generations. Combine that with the rumours that Nova Lake/Coyote Cove won't see major (or any) P-core clockspeed updates, and you'll have a situation where Nova Lake will struggle with ST performance (as well as MT performance, particularly in the range of 8-16 threads).