Question Zen 6 Speculation Thread

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511

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While others seem to have addressed this question rather well, it seems that (for now) Intel hasn't progressed much IPC-wise with thier P cores over the last few generations. Combine that with the rumours that Nova Lake/Coyote Cove won't see major (or any) P-core clockspeed updates, and you'll have a situation where Nova Lake will struggle with ST performance (as well as MT performance, particularly in the range of 8-16 threads).
NVL is a proper tick tock combined Process+IPC double digits IPC is pretty much guaranteed like 14-18% similar to previous tocks
 

Fjodor2001

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While others seem to have addressed this question rather well, it seems that (for now) Intel hasn't progressed much IPC-wise with thier P cores over the last few generations. Combine that with the rumours that Nova Lake/Coyote Cove won't see major (or any) P-core clockspeed updates, and you'll have a situation where Nova Lake will struggle with ST performance (as well as MT performance, particularly in the range of 8-16 threads).
What you mentioned is also true for Zen. Remember the whole Zen 5% discussion?
 

Thunder 57

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NVL is a proper tick tock combined Process+IPC double digits IPC is pretty much guaranteed like 14-18% similar to previous tocks

Tick tock hasn't been a thing for a long time now.

What you mentioned is also true for Zen. Remember the whole Zen 5% discussion?

Zen 5% was server first and did well there. Gamers and public opinion were pissed it didn't reach 32% as claimed by some.

Gaming is a low IPC Workload it's more latency and Cache sensitive...

And Intel has crap cache don't see them picking up a bunch.
 

Markfw

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Zen 5% was server first and did well there. Gamers and public opinion were pissed it didn't reach 32% as claimed by some.
It has been proven that Zen 5 in some tests are faster by as much as 56%.

Not that is in one area, yes, so don't beat me up. but in many tests is has surpassed the 5%. I could look up the phoronix tests, but not at the moment.
 

DrMrLordX

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NVL is a proper tick tock combined Process+IPC double digits IPC is pretty much guaranteed like 14-18% similar to previous tocks

When was the last time Intel actually made good on that? P-cores have struggled since Alder Lake.

What you mentioned is also true for Zen. Remember the whole Zen 5% discussion?

It's a meme born of some gaming benchmarks that (surprise surprise) no longer matter thanks to the 9800X3D. Meanwhile Turin says hello:


or if you prefer a desktop CPU comparison, Phoronix has something to say about it:


Looks more like Zen17.8%.

Tick tock hasn't been a thing for a long time now.

Yup.

Gamers and public opinion were pissed it didn't reach 32% as claimed by some.

That was due to some leakers (cough cough who could they be) going nuts on OEM numbers in server workloads.
 

Fjodor2001

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Looks more like Zen17.8%
That’s for regular Linux desktop and non-X3D, so N/A in this case.

Because the whole discussion started about the impact of bLLC, and whether NVL-S with bLLC will be able to compete with Zen6 X3D.
It's a meme born of some gaming benchmarks that (surprise surprise) no longer matter thanks to the 9800X3D.
So what’s the real % for Zen5 gaming, if not Zen 5%?
 

511

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When was the last time Intel actually made good on that? P-cores have struggled since Alder Lake.
ARL Fabric/LLC botched Lion Cove and Skymont
And Intel has crap cache don't see them picking up a bunch.
Yup RPL had real good memory latency the L3 was okayish
Tick tock hasn't been a thing for a long time now.
It has been kind of being followed

Intel 7 -> Intel 4/3
Golden Cove -> Redwood Cove
Gracemont -> Crestmont
N3B -> 18A
Lion -> Cougar
Skymont -> Darkmont

On TSMC Node they don't need to derisk the process causes TSMC does it for them but on their nodes they need to.
 

DrMrLordX

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That’s for regular Linux desktop and non-X3D, so N/A in this case.

Umm okay:


Zen34%?!?

The whole discussion started about the impact of bLLC, and whether NVL-S with bLLC will be able to compete with Zen6 X3D.

And it won't, because Intel's cache is slow and adding more slow cache isn't really a good solution.

So what’s the real % for Zen5 gaming, if not Zen 5%?

Depends on the title, but:


Around 8% faster on average. Seems consistent with TPU which showed around 7.3% @ 720P:

 
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Doug S

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It's word soup that bears no relation to the reality of designing prime cores for Fin/NanoFlex-enabled nodes.

Well if you weren't allergic to a "wall of text" you could explain to us, in detail, where and why I'm wrong. But nope, with you, its "trust me bro". That shtick has gotten old.
 
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reaperrr3

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Zen 7-8% is honestly not much more impressive than Zen 5%. 🤣
At Computerbase.de, where they were testing different games and at 1080p instead of 720p, it was 13-14%.

And how do you know this will be the case for NVL-S with bLLC too?
This has been explained before, but one of the reasons is physical design.

The only reason AMD can do such big L3s at such low latencies at all is the vertical stacking, because thanks to the layers being very thin, physical distance to the farthest SRAM cells doesn't increase much, despite the tripling of the total L3.

A monolithic massive 2D cache like Intels bLLC has more distance/cells to cover from corner to corner, making it much harder to get high clocks and low latency under the same hood without running into heat/power/clock/degradation issues.

The other aspect is, both vendors use exclusive cache designs nowadays, where L3 is only accessed when some data isn't found in the L2, and since Intel's P-cores have 3x as much L2 (and that extra L1.5D), they don't need to access L3 as often and as early, while also going through higher total latency before doing so (Intel's L2 has higher latency than AMD's).

Basically, Intel L3 is accessed less often for small stuff, and takes longer to access for big stuff, both by design.
Making it bigger won't improve either, that only reduces the even slower memory accesses.
 

Fjodor2001

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Ok, but what you described was for ARL-S, I assume.

Do we know what changes will be coming for the caches in NVL-S? Are they expected to work exactly the same as in ARL-S, and if so why?
 
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511

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And it won't, because Intel's cache is slow and adding more slow cache isn't really a good solution.
The only problem is L3 L2/L1 is fine if anything their L1/L2 have been pulling the weight to mitigate Slow L3
Ok, but what you described was for ARL-S, I assume.

Do we know what changes will be coming for the caches in NVL-S? Are they expected to work exactly the same as in ARL-S, and if so why?
PTL has fixed the L3
 

DrMrLordX

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Ok, but what you described was for ARL-S, I assume.

The horizontal stacking latency will apply to Nova Lake-S. Presumably the size of the L2 of Nova Lake-S will also be relevant as it is in Arrow Lake.

As far as 7-8% not being that much different . . . okay? Somehow Zen5 remains the fastest gaming CPU out there while also enjoying an impressive lead over Zen4 in everything that isn't (certain) games. Including the X3D parts where the 9800X3D has a big lead over the 7800X3D in non-gaming tasks. bLLC isn't going to solve that for Nova Lake-S, not on its own.
 
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Josh128

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Member callouts are against the rules.
Im sure MarkFW is about to nuke this Intel tangent in the Zen 6 thread, but new PTL CPU-z leaks show almost no IPC increase (in CPU-z) vs Raptor Lake P cores. ~165 points/GHz, based on two different runs, which match. This one is at 3GHz.


1763816310585.png
 
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adroc_thurston

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511

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ondma

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That’s for regular Linux desktop and non-X3D, so N/A in this case.

Because the whole discussion started about the impact of bLLC, and whether NVL-S with bLLC will be able to compete with Zen6 X3D.

So what’s the real % for Zen5 gaming, if not Zen 5%?
Zen 5 x3D is significantly faster than Zen 4 x3D because they redesigned the cache so it dissipates heat more efficiently, allowing them to clock it close to the vanilla chips, which helps both gaming and productivity. Not sure the exact figures, but I think 10 to maybe even 20 percent faster for the Zen 5 x3D chips. I know AMD has tried to tweak vanilla Zen 5 for gaming, but don' know how much additional performance they were able to eek out. I think the gain for vanilla Zen 5 is still lower than 10%.

As for NVL/Zen 6, I think AMD will still have a significant advantage because they will have a 12 core single CCD vCache chip. It should be an absolute beast for gaming, especially if the predictions of higher clocks pan out. NVL will be limited to a single 8 core vCache chiplet, probably w/o hyperthreading, so unfortunately, I dont see it being competitive.
 
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AMDK11

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It has been proven that Zen 5 in some tests are faster by as much as 56%.
Zen5 IPC:
Marketing gains from +10% to +35% (average +16%)

Int gains average +13%, and FP gains average +25%.

9950X AVX512(ON) average +56%
7950X AVX512(ON) average +41%
 
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regen1

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The horizontal stacking latency will apply to Nova Lake-S. Presumably the size of the L2 of Nova Lake-S will also be relevant as it is in Arrow Lake.

As far as 7-8% not being that much different . . . okay? Somehow Zen5 remains the fastest gaming CPU out there while also enjoying an impressive lead over Zen4 in everything that isn't (certain) games. Including the X3D parts where the 9800X3D has a big lead over the 7800X3D in non-gaming tasks. bLLC isn't going to solve that for Nova Lake-S, not on its own.
9000 series X3Ds are generally the fastest gaming CPUs for now but
non-X3D 9000 series are about the same mean gaming performance as ARL-S counterparts. ARL-S has latency issues with ring/D2D/NGU/L3.
For NVL-S the design should be optimized for improved latency.

With same design undoubtedly 3D stacked L3 is better for latency than just horizontal increase in L3 capacity.
Regarding gaming perf, NVL bLLC versions' 144MB L3(vs the standard 36MB) should help cut memory access by a good amount which should result in decent uplift for many games relatively, though the question is how well NVL-S bLLC fares against others esp. some gaming oriented X3D SKUs in gaming and other tasks.
 

Thunder 57

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9000 series X3Ds are generally the fastest gaming CPUs for now but
non-X3D 9000 series are about the same mean gaming performance as ARL-S counterparts. ARL-S has latency issues with ring/D2D/NGU/L3.
For NVL-S the design should be optimized for improved latency.

With same design undoubtedly 3D stacked L3 is better for latency than just horizontal increase in L3 capacity.
Regarding gaming perf, NVL bLLC versions' 144MB L3(vs the standard 36MB) should help cut memory access by a good amount which should result in decent uplift for many games relatively, though the question is how well NVL-S bLLC fares against others esp. some gaming oriented X3D SKUs in gaming and other tasks.

It's not just ARL that has had issues with L3. It goes back to ADL IIRC. Intel hasn't been able to fix it, as it actually got worse going to ARL. I have no faith in them overcoming all the hurdles you mentioned in one go.