Question Zen 6 Speculation Thread

[511]

Oh noes they're all max Vt's with 3-2 finpop for Apple, even.
It's a very consistent crankage, amounted to about 40% fmax M1 -> M4 with a single full node.

40% Fmax was only possible cause they had room to spare not entirely due to node

 

[adroc_thurston]

40% Fmax was only possible cause they had room to spare not entirely due to node

Not really, they were already at zoom Vt's.
Rest was organic node CAGR, perf cells and 3-2 finpop.
Guess what? AMD can and will use all three to do just the same!

 

[Josh128]

N2X is maybe 2 bins of speed if you're lucky.
N3X was 1.

6.5 is a 14% fmax bump. That's nothingburger.
QC got 19% off a single shrink and a wee bit of Vmax cranking.
Apple got 31% doing just the same.

N2X will allow +10% fmax over N2 according to TSMCs own slides.

14% is not a nothingburger, its actually a pretty big burger when you consider the largest gen on gen freq increase Ryzen has ever achieved was 16%, and that was only achieved once in 6 generations-- in 5950X to 7950X. The next biggest uplift, going from 12nm to 7nm, only got them 9% on paper (4.7 3950X vs 4.3 2700X). That uplift was even less in practice than on paper. That also completely ignores that the physical challenges of switching transistors at a much higher absolute frequency, at the high end of C band approaching X band.

 

[adroc_thurston]

N2X will allow +10% fmax over N2 according to TSMCs own slides.

It's an overdrive option and it's fake.
You get 2 bins of speed. N3X is one bin of speed. Pretty simple on average.

14% is a pretty big burger when you consider the largest gen on gen freq increase Ryzen has ever achieved was 16%, and that was only achieved once. Going from 12nm to 7nm only got them 9% on paper (4.7 3950X vs 4.3 2700X). That uplift was even less in practice than on paper.

Wordswords, Zen4 was 13% off a single shrink. They didn't even touch the perf options.

 

[Josh128]

It's an overdrive option and it's fake.
You get 2 bins of speed. N3X is one bin of speed. Pretty simple on average.

Wordswords, Zen4 was 13% off a single shrink. They didn't even touch the perf options.

And? Zen 2 was 9% off of a double shrink.

N2X is not fake, its a very specific technology-- and the fact that its not available until '27 supports that.

 

[adroc_thurston]

And? Zen 2 was 9% off of a double shrink.

a) single shrink (N10 was a meme halfnode)
b) ancient history

N2X is not fake, its a very specific technology-- and the fact that its not available until '27 supports that.

The 10% "perf" thing is fake (you get more like 3-5%) and in any case, none of those designations apply to N2 AMD uses.

 

[adroc_thurston]

At least we've moved from "it's N3p!!!1111" to "it won't clock" kinda schizoposting. Adorable.

 

[OneEng2]

6.5 is a 14% fmax bump. That's nothingburger.
QC got 19% off a single shrink and a wee bit of Vmax cranking.
Apple got 31% doing just the same.

I think you are very optimistic about drastically increasing clocks on x86 that we have seen hide nor hair of for over a decade. I think your optimism is cute though.

40% Fmax was only possible cause they had room to spare not entirely due to node

Agree.

N2X will allow +10% fmax over N2 according to TSMCs own slides.

... and even that is at the expense of density and/or power. Lets not forget that Zen 6 by AMD's own words is "DC First design". I suspect that Zen 6 will be optimized for power efficiency. Even on desktop we are seeing the high core count Zen 5 reach socket max as the limiting factor. Adding 50% more cores will certainly place even more focus on power efficiency.

Of course, it is always possible that they make a desktop version that is designed to clock scale .... but good luck getting all 24 cores up to speed under the power limit.

At least we've moved from "it's N3p!!!1111" to "it won't clock" kinda schizoposting. Adorable.

What is adorable is your supreme confidence in a clock speed increase the like's of which we haven't seen in quite some time .... and at a time when improvements from node to node are drastically decreasing.

 

[adroc_thurston]

I think you are very optimistic about drastically increasing clocks on x86 that we have seen hide nor hair of for over a decade

14% speed bump is the least drastic thing you can get outta full node.
But you get two. Wonderful isn't it.

and even that is at the expense of density and/or power

Nope. But you pay more.

What is adorable is your supreme confidence in a clock speed increase the like's of which we haven't seen in quite some time

You saw 13% fmax bump 3 years ago.

... and at a time when improvements from node to node are drastically decreasing

They aren't, you're getting 10-15% speed a full node from now on till the end of times.
SRAM and analog scaling died off at least.

 

[511]

They aren't, you're getting 10-15% speed a full node from now on till the end of times.

that's iso voltage not peak Fmax and still lower than what one would get

 

[adroc_thurston]

that's iso voltage not peak fmax

That's the same thing.
Vmax isn't being dialed down in any real way.

 

[511]

That's the same thing.
Vmax isn't being dialed down in any real way.

Vmax is dialed down with GAAFET as they have lower Voltage than FinFet

 

[adroc_thurston]

Vmax is dialed down with GAAFET as they have lower Voltage than FinFet

Nope.
We're still at 1.4v-ish for maximum safe operation.

 

[511]

Nope.
We're still at 1.4v-ish for maximum safe operation.

N3 had 1.5V ish from what i remember or was it higher still -0.1V

 

[adroc_thurston]

N3 had 1.5V ish from what i remember still -0.1V

AMD doesn't ship above 1.45v so it's w/ever. Zero changes on that front.

 

[511]

AMD doesn't ship above 1.45v so it's w/ever. Zero changes on that front.

good for them more voltage is injurious to your product

 

[inquiss]

I think you are very optimistic about drastically increasing clocks on x86 that we have seen hide nor hair of for over a decade. I think your optimism is cute though.

This comment is, errr, interesting. When Apple released their latest processor with their highest clocks ever, would your reasoning have been that it's impossible because we hadn't seen it before?

Not a genuine question, of course, just highlights how absurd the reasoning in comment is...

 

[adroc_thurston]

When Apple released their latest processor with their highest clocks ever

It's whatever even.
QCOM ships a 5G chungus (well, 2.2mm^2 is chungus enough) on a 2-2 N3x.

 

[OneEng2]

This comment is, errr, interesting. When Apple released their latest processor with their highest clocks ever, would your reasoning have been that it's impossible because we hadn't seen it before?

Not a genuine question, of course, just highlights how absurd the reasoning in comment is...

Note: I am addressing x86, not apple. In specific, we are talking about Zen 6 which for all intents and purposes at the core level is only a minor change from Zen 5.

Zen 5 is already power limited at max core count (not frequency limited). I have speculated that in the future, we may have 1-4 cores that are "super clock" cores designed expressly to clock to very high speeds for low thread count situations. No one is saying anything like that for Zen 6 and in fact, AMD is specifically saying Zen 6 is a "server first" design.

This leads me to believe that the double process shrink 5nm class to 2 nm class will be used primarily to boost power efficiency allowing more cores to have higher performance at the same power window vs maximum frequency designs.

I am guessing Zen 6 top bin will max out at 6.5Ghz or less based on this thought process.

 

[adroc_thurston]

that the double process shrink 5nm class to 2 nm class will be used primarily to boost power efficiency

You do understand that perf/power relationship isn't mutually exclusive