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Question Zen 6 Speculation Thread

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OneEng2 said:
I find it HIGHLY unlikely that AMD is going to drop EPYC Zen 6 full core count down to 96 cores.

I also find it IMPOSSIBLE to believe that AMD will reduce the core count on their EPYC dense. The entire purpose of the dense version is for cloud computing that doesn't utilize the L3 very well and where max core count rules.

I am thinking this is a little too far off the side of reason as well.

It's just my speculation at this time, but I find it much more likely that AMD will lean into chiplets and IOD technology in the next generations of processors. This will lead to smaller die sizes and more complex combinations of IOD's.

This gives AMD the best combination of cost reduction and scalability.

I believe a 32c CCD is technically possible, but it may well be economically inferior. Think of it this way....

AMD can EITHER create fewer VERY expensive CCD's and have a less complex packaging having fewer IOD's OR they can create MORE less expensive CCDs and use more IOD's.

I see no down side to the scaleable approach and many advantages.

Scaling via an IOD that has 4 channel memory allows AMD to scale memory channels along with processor cores keeping the system in balance.

Each generation AMD gets to decide what memory technology they will support the platform on, select the number of cores in a CCD that can be fed from that memory, then create an IOD that matches the number of channels needed to the number of CCD's supported.

Scaling of cores then becomes something that is only limited by the socket power and max memory channels supported by the socket design.

These kinds of decisions are my daily bread and butter. From a business standpoint, this looks pretty appealing to me.

I even doubt that there is a performance hit by putting fewer cores on a CCD and having more IOD's vs having fewer IOD's and having more cores on the CCD as work is scheduled by thread in the OS.
Click to expand...
🤣
 
SP5 power limit is around 500W I believe. The new SP7 expected for EPYC Zen 6 is going to be around 1000W.

It isn't reasonable to expect core counts to go DOWN from Turin models to Zen 6 models. I don't care what rumor you are parroting.

Additonally, having only bumped memory speeds from 6000MT to 6400MT means that they will absolutely need more IOD's. The rumor is up to 16 memory channels. Each IOD has 4 channels so that would mean 4 IOD's.

4 IOD's each having 4 CCD's will be the max config for BOTH EPYC standard (Zen 6) and EPYC Dense (Zen 6c) configurations. The difference will be in the number of cores on the CCD.

Someone feel free to knock holes in this line of argument.
 
OneEng2 said:
SP5 power limit is around 500W I believe. The new SP7 expected for EPYC Zen 6 is going to be around 1000W.

It isn't reasonable to expect core counts to go DOWN from Turin models to Zen 6 models. I don't care what rumor you are parroting.

Additonally, having only bumped memory speeds from 6000MT to 6400MT means that they will absolutely need more IOD's. The rumor is up to 16 memory channels. Each IOD has 4 channels so that would mean 4 IOD's.

4 IOD's each having 4 CCD's will be the max config for BOTH EPYC standard (Zen 6) and EPYC Dense (Zen 6c) configurations. The difference will be in the number of cores on the CCD.

Someone feel free to knock holes in this line of argument.
Click to expand...

In one of the subsequent videos on MLID (post his Zen 6 Vienna video). I tried to find it but could not. It is buried deep in the video, hard to find.

Original video ha each IOD with 2 CCD connections and presumably 4 memory channels.
Subsequent video showed 2 of the IODs merged, with IOD having 4 CCD connections and presumably 8 memory channels.

But that does not address your main point, of why AMD would go down:
- from 16 Zen 5 CCDx x 8 cores = 128 cores
- to 8 Zen 6 CCDs x 12 cores = 96 cores

It seems like a split in Venice product line between highest per thread performance and highest number of simultaneous threads. Which is not a crazy idea...
- from with 8 CCDs x 12 cores
 
OneEng2 said:
SP5 power limit is around 500W I believe. The new SP7 expected for EPYC Zen 6 is going to be around 1000W.

It isn't reasonable to expect core counts to go DOWN from Turin models to Zen 6 models. I don't care what rumor you are parroting.

Additonally, having only bumped memory speeds from 6000MT to 6400MT means that they will absolutely need more IOD's. The rumor is up to 16 memory channels. Each IOD has 4 channels so that would mean 4 IOD's.

4 IOD's each having 4 CCD's will be the max config for BOTH EPYC standard (Zen 6) and EPYC Dense (Zen 6c) configurations. The difference will be in the number of cores on the CCD.

Someone feel free to knock holes in this line of argument.
Click to expand...
It isn't going down? SP6 -> SP8 is 64->96 cores, SP5->SP7 is 192->256 cores.
 
Kepler_L2 said:
It isn't going down? SP6 -> SP8 is 64->96 cores, SP5->SP7 is 192->256 cores.
Click to expand...

I am getting completely confused. IIRC, SP6 was the Siena platform, lower cost, socket used for "dense only" CCDs.

Is the successor to Siena, SP8 now full core, 8x12 = 96 cores? If SP8 were to continue the "dense only" approach, it would use the 32 core CCDs, and 3 CCDs seems (in fact is) an odd number.
 
Joe NYC said:
I am getting completely confused.
Click to expand...
very simple.
Joe NYC said:
SP6 was the Siena platform, lower cost, socket used for "dense only" CCDs.
Click to expand...
Sorano too.
Joe NYC said:
Is the successor to Siena, SP8 now full core, 8x12 = 96 cores?
Click to expand...
It also has dense and networking options.
SP8 is their catchall ms server platform.

tl;dr they have more server share and thus can afford running more server platforms concurrently
 
adroc_thurston said:
very simple.

Sorano too.

It also has dense and networking options.
SP8 is their catchall ms server platform.

tl;dr they have more server share and thus can afford running more server platforms concurrently
Click to expand...

Do the SP7 and SP8 support the same number of CCDs? IODs?

Uzzi posted on Twitter that they support the same number of PCI channels...

There may be an obvious answer, but I am still missing it.
 
Joe NYC said:
I am getting completely confused. IIRC, SP6 was the Siena platform, lower cost, socket used for "dense only" CCDs.

Is the successor to Siena, SP8 now full core, 8x12 = 96 cores? If SP8 were to continue the "dense only" approach, it would use the 32 core CCDs, and 3 CCDs seems (in fact is) an odd number.
Click to expand...
Here is the breakdown of Venice SP7 and SP8:
  1. SP8: 96-core (N3P, 8x12-core, 384MB OR N2, 3x32-core, 384MB) + 1 IOD 8-channel
  2. SP8: 128-core (N2, 4x32-core, 512MB) + 1 IOD 8-channel
  3. SP7: 192-core (N2, 6x32-core, 768MB) + 2 IOD 16-channel
  4. SP7: 256-core (N2, 8x32-core, 1024MB) + 2 IOD 16-channel
 
Last edited:
Tigerick said:
Here is the breakdown of Venice SP7 and SP8:
  1. SP8: 96-core (N3P, 8x12-core, 384MB) + 1 IOD 8-channel
  2. SP8: 128-core HP (N2, 4x32-core, 512MB) + 1 IOD 8-channel
  3. SP7: 192-core HP (N2, 6x32-core, 768MB) + 2 IOD 16-channel
  4. SP7: 256-core HD (N2, 8x32-core, 1024MB) + 2 IOD 16-channel
Click to expand...
that's... made up? why are you confident in N3 for 12C classic? why is there a random jump from HP to HD in 192->256? reduce+reuse is like the whole motto of chiplets.
 
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