Question Zen 6 Speculation Thread

[Joe NYC]

https://twitter.com/x/status/1919702960273326131

Looks like Venice and Medusa may share the same N2 12C CCD after all

So looks like 1 IOD may have 4 CCDs connected to it, 2 on each side, and 2 IODs are shown, which would be 8 CCDs x 12 cores = 96 cores?

Edit: Since Turin has 128 cores, 3 of the IO Dies could add up to 144 cores, which could be more likely for the core count.

But if there are to be 16 memory channels, then 2 or 4 IODs would make more sense.

 

[Kepler_L2]

So looks like 1 IOD may have 4 CCDs connected to it, 2 on each side, and 2 IODs are shown, which would be 8 CCDs x 12 cores = 96 cores?

Edit: Since Turin has 128 cores, 3 of the IO Dies could add up to 144 cores, which could be more likely for the core count.

But if there are to be 16 memory channels, then 2 or 4 IODs would make more sense.

Would be weird to go backwards on core count, but maybe they are just targeting maximum performance per core for regular Venice. 96 cores @ 6GHz @ 600W maybe? 😛

 

[Saylick]

Link didn't work for me, but I'll take your word for it 🙂.

If that is the case, then:

• Desktop is assured to be N2 CCD
• Likely 192c for the high performance Turin
• Turin D @ ~240-288 Zen 6c cores (20-24 CCD's)?

Here's the image from the Xitter post, which shows 12 core CCDs with 48 MB L3 cache. It also looks like there's multiple IODs on package.

 

[adroc_thurston]

Would be weird to go backwards on core count, but maybe they are just targeting maximum performance per core for regular Venice. 96 cores @ 6GHz @ 600W maybe? 😛

remember there are two venice platforms

 

[MS_AT]

remember there are two venice platforms

As in dense and normal? Or two venice normal platforms?

 

[adroc_thurston]

As in dense and normal? Or two venice normal platforms?

Yes and yes.
There's Venice-classic and Venice-dense and then there's SP7 and SP8 venice, which is high-end/mainstream split akin to Intel's AP/SP duality.
Plus SP8 has let's say, interesting options for other markets.

 

[OneEng2]

So looks like 1 IOD may have 4 CCDs connected to it, 2 on each side, and 2 IODs are shown, which would be 8 CCDs x 12 cores = 96 cores?

Edit: Since Turin has 128 cores, 3 of the IO Dies could add up to 144 cores, which could be more likely for the core count.

But if there are to be 16 memory channels, then 2 or 4 IODs would make more sense.

Turin Classic
1 IOD = 4 CCD = 48 cores
2 IOD = 8 CCD = 96 cores
3 IOD = 12 CCD = 144 cores
4 IOD = 16 CCD = 192 cores

Turin Dense
Lets say they can get 25% more cores in the same die so 1 CCD = 16 cores (round up).

Max Turin Dense then is 256c

 

[adroc_thurston]

Turin Classic
1 IOD = 4 CCD = 48 cores
2 IOD = 8 CCD = 96 cores
3 IOD = 12 CCD = 144 cores
4 IOD = 16 CCD = 192 cores

That's not how any of that works.

Lets say they can get 25% more cores in the same die so 1 CCD = 16 cores (round up).

It's a 32c CCD(ish).

 

[yuri69]

Given Venice Dense goes for 32c CCD, it feels natural to make a 16c CCD too. Plus reuse client 12c CCD for lower-end.

 

[fastandfurious6]

If both AMD and TSMC staged the PR event announcing Zen 6 (EPYC) is the leading product on N2, it does not make a lot of sense for this chip to ship as ~ #10 product on N2 (almost a year later), rather than as #1 or close to #1.

yeah literally everything points to that reality

basically chip vendors have clear visibility into performance even 16 months earlier than release date


but how do they know the competitors perf? release after release in popular benchmarks the numbers are very close between competing chips

 

[fastandfurious6]

[zen6c]
It's a 32c CCD(ish).

how did they add 20 entire cores onto dense zen6c ccd from full zen6 12c ccd??

crazy stuff

 

[adroc_thurston]

how did they add 20 entire cores onto dense zen6c ccd from full zen6 12c ccd??

Its a shrink, also stuff.

 

[Hulk]

I hope AMD brings down idle power draw to Intel levels for Zen 6.

 

[Hulk]

Its a shrink, also stuff.

I was confused until I read the "stuff" part. Now it's crystal clear how they will do it.

 

[fastandfurious6]

zen 6 secret sauce

 

[fastandfurious6]

so like, intel nova lake sounds crazy with 52 frankenstein P+E+LP+ACME cinebench cores,

but AMD already prepares 32+32cores dense zen6c client chip?

I'm stuff

 

[adroc_thurston]

but AMD already prepares 32+32cores dense zen6c client chip?

You're not getting any core spam from AMD.

 

[LightningZ71]

They are going to slowly ease in a few cores every now and then, and you are going to have to like it that way.

 

[Joe NYC]

I hope AMD brings down idle power draw to Intel levels for Zen 6.

That is likely a function of IO die, which will be new, eliminating SerDes. Also, likely on new process node(s)

Also, it is likely that the new IO Die will have LP cores, which will allow shutting off the CCDs entirely, for more power savings.

 

[fastandfurious6]

if the LP cores can do snappy web browsing/core OS stuff with some small burst from full cores that will be big win for mobile

web surfing battery life
Halo-9955hx = 10+ hours
intel 275hx = 5-7hrs depending on laptop
7945hx = 4hrs max

assuming non-halo-9955hx will have around 5hrs but zen6 likely reaching 20+


if cpu scheduling gets advanced enough to offload standard OS loops to separate LP cores that will be big

 

[511]

if the LP cores can do snappy web browsing/core OS stuff with some small burst from full cores that will be big win for mobile

web surfing battery life
Halo-9955hx = 10+ hours
intel 275hx = 5-7hrs depending on laptop
7945hx = 4hrs max

assuming non-halo-9955hx will have around 5hrs but zen6 likely reaching 20+


if cpu scheduling gets advanced enough to offload standard OS loops to separate LP cores that will be big

There is no LP-E on Zen 5 it's on Zen 6 and also Intel is going LP-E with NVL across all SKUs and we all know how Skymont is with LP-E.

 

[OneEng2]

It's a 32c CCD(ish).

A 32c Zen 6c CCD would be approximately 170mm2. You really think this is achievable within the constraints of a business case on the most expensive process node available?

The math doesn't work IMO. I know that you simply rely of "stuff" as your logic (strange for a forum filled with tech heavy posters). Care to explain how you feel this is possible?

I did make a mistake on Zen 6c EPYC Dense though.

Current die is 16c on 3nm. A 25% die shrink gives you a 20 core CCD (if AMD wants to stay in the same ~85mm2 CCD die). So a 4 IOD part would be a 320c/640t.

how did they add 20 entire cores onto dense zen6c ccd from full zen6 12c ccd??

crazy stuff

How did the fit it into a die that they can manufacture profitably! 😉. The current 3nm CCD has 16 Zen 5c cores (stripped cache from full Zen 5 so it's smaller as well). Still, the N2 die shrink only gets you another 25% if you want to stay at the same die size for the CCD.

Its a shrink, also stuff.

Ok. The shrink gets you 25% Care to explain how big the die would be in YOUR calculation?

I was confused until I read the "stuff" part. Now it's crystal clear how they will do it.

Ahh. It's the "Stuff"! Now the math makes perfect sense to me Hulk. I left dy/dstuff out of my differential equation! Must be old age 😉.

 

[511]

A 32c Zen 6c CCD would be approximately 170mm2. You really think this is achievable within the constraints of a business case on the most expensive process node available?

The math doesn't work IMO. I know that you simply rely of "stuff" as your logic (strange for a forum filled with tech heavy posters). Care to explain how you feel this is possible?

I did make a mistake on Zen 6c EPYC Dense though.

Current die is 16c on 3nm. A 25% die shrink gives you a 20 core CCD (if AMD wants to stay in the same ~85mm2 CCD die). So a 4 IOD part would be a 320c/640t.

How did the fit it into a die that they can manufacture profitably! 😉. The current 3nm CCD has 16 Zen 5c cores (stripped cache from full Zen 5 so it's smaller as well). Still, the N2 die shrink only gets you another 25% if you want to stay at the same die size for the CCD.

Ok. The shrink gets you 25% Care to explain how big the die would be in YOUR calculation?

Ahh. It's the "Stuff"! Now the math makes perfect sense to me Hulk. I left dy/dstuff out of my differential equation! Must be old age 😉.

N2 shrink only gets you 1.2 also N4P to N3E is 1.3 ish that is for same design and this doesn't take FinFlex into account

 

[reaperrr3]

A 32c Zen 6c CCD would be approximately 170mm2. You really think this is achievable within the constraints of a business case on the most expensive process node available?

What?
A 75mm² N2 CCD that will be used all the way down to 250$ products is fine, but 8 ~170mm² CCDs for 10k+ server CPUs is somehow not viable from a business perspective? 🙄

Given how solid N2 appears to be in terms of defect rate, 170mm² is still quite small and would have incredibly low defect rates, where most partially defective CCDs can be used in lower SKUs.

Don't dismiss this 32c just because adroc is one of the people claiming it's real...
You make it sound like AMD doesn't have crazy good margins in their server CPUs already, and the CCD silicon is only a relatively small part of the cost anyway.

I'm also not convinced the 32c will be more than twice the size of the 12C.
The 32c CCD uses denser cores, possibly only 64MB L3, and won't have twice the IF connection stuff of the 12C CCD, either.

 

[adroc_thurston]

A 32c Zen 6c CCD would be approximately 170mm2

Again, you're not thinking it the right way.

The shrink gets you 25% Care to explain how big the die would be in YOUR calculation?

You shouldn't even bother.

So a 4 IOD part would be a 320c/640t.

what's a 4 IOD and how do I escape route 16 memory channels outta datboi.