Question Zen 6 Speculation Thread

[Fjodor2001]

No, it is purely technical. Logos do not matter. What AMD and Intel are doing is suboptimal, cost-saving methods for reuse.

So far when Apple does that for their biggest chips only because it would simply be too big to fit in reticle and unyieldable.

Not sure what you mean by that. Apple is in their own ecosystem, so they are in a special monopoly case.

For Intel/AMD, it's Windows on DT/mobile and a price competition.

 

[gdansk]

Not sure what you mean by that. Apple is in their own ecosystem, so they are in a special monopoly case.

For Intel/AMD, it's Windows on DT/mobile and a price competition.

Laptops do not need glue. That's all poverty cope. You can build an efficient 600mm² laptop chip if you're not poor like Intel and AMD. And it would be better too. Notably also not 50+ cores... weird.

Where you cannot effectively build a big chip without glue is server. And lo - everyone in the server market uses glue. That is not the case for laptops.

 

[adroc_thurston]

They'll have to match whatever idiotic power limit Intel is cooking up and I doubt they will given AM5 socket guidance to date.

They just have much more efficient IP.

And that'll outperform NVL-S 52C in MT?

Probably.
You've seen Venice already, and medusaDT is 50% moar cores instead of 33%.

So what specs for CPU + iGPU + NPU are you expecting for Zen6 on mobile/laptop/DT? And why are you expecting that to outperform the offer from Intel NVL, including in perf/watt?

Idk they're just gonna be better.

Just as an example: What iGPU are you expecting on Zen6 DT that'll be better than what NVL-S will have?

Whatever tiny RDNA3.5 blob they ship.

 

[adroc_thurston]

Laptops do not need glue. That's all poverty cope. You can build an efficient 600mm² laptop chip if you're not poor like Intel and AMD

This is the most idiotic statement you've made since Apple is moving to 2.5D SoIC like next year.

 

[gdansk]

This is the most idiotic statement you've made since Apple is moving to 2.5D SoIC like next year.

Eventually cost hits everyone.
But there's no reason for Intel at their tiny sizes except for reuse. It isn't helping consumers.
And Strix Halo is a perfect example of how disaggregation doesn't help anything if the IP still sucks. There is never a *competitive* chance for reuse.

 

[Fjodor2001]

Probably.
You've seen Venice already, and medusaDT is 50% moar cores instead of 33%.

Not sure if serious.

Idk they're just gonna be better.

It's the idk part I'll take with me.

Whatever tiny RDNA3.5 blob they ship.

GPU core count matter too you know. Since several years AMD has been way behind Intel in iGPU perf on DT. Why do you think that will change with Zen6 / NVL-S?

 

[adroc_thurston]

Eventually cost hits everyone.

Reuse is also nice.

But there's no reason for Intel at their tiny sizes except for reuse

Not much reuse there either. It's weird.

And Strix Halo is a perfect example of how disaggregation doesn't help anything if the IP still sucks.

Meds

 

[gdansk]

Meds

I'm not wrong. The configuration exists as a proof-of-concept. Nothing seems to have survived that shares chips with it.

 

[gdansk]

I speculate that 24C Z6 DT will be competitive with 52C NVL on e.g. compilation. With in 90±5% in Linux kernel compile w/ gcc at the same power limit.

And it should use much less silicon to achieve that. That isn't because I have any idea of the performance of the parts, rather we know many of the limitations on compilation performance and they will both end up similar in that respect. Linking, effective memory bandwidth, etc...

 

[Doug S]

This is the most idiotic statement you've made since Apple is moving to 2.5D SoIC like next year.

It sounds like that's for the Pro & Max only not the base. This wasn't driven by their laptop (or desktop) economics, it was driven by their need to build servers. Rather than making an AI server specific chip with tons of GPU cores and few CPU cores, and a general purpose server specific chip with tons of CPU cores and zero GPU cores it made sense to split up the CPU and GPU stuff. That would allow them to mix n match those parts to build AI servers, CPU servers, Pro, Max, Ultra and who knows maybe we'll finally see the long rumored but never realized 'Extreme'. Even if they wanted to do dedicated designs for the servers they'd still have had to go to Ultra style chiplets because they likely want to exceed the reticle limit for the same reason Nvidia does.

It would also allow them the option of offering a wider variety of SKUs for the Max, i.e. a "lot more CPU cores" instead of "a lot more GPU cores" if they think there's sufficient demand for that. That is if they're even willing to add SKUs to address it, since Apple has always avoided having too many choices both for manufacturing efficiency and inventory reasons, and because academic marketing research has shown again and again that too much choice makes consumers less likely to buy.

 

[CakeMonster]

Any guesses on sweet spot memory speed for Zen6?

 

[adroc_thurston]

Any guesses on sweet spot memory speed for Zen6?

Well it ships 8000 so 8000 it is.

 

[adroc_thurston]

It sounds like that's for the Pro & Max only not the base. This wasn't driven by their laptop (or desktop) economics, it was driven by their need to build servers. Rather than making an AI server specific chip with tons of GPU cores and few CPU cores, and a general purpose server specific chip with tons of CPU cores and zero GPU cores it made sense to split up the CPU and GPU stuff. That would allow them to mix n match those parts to build AI servers, CPU servers, Pro, Max, Ultra and who knows maybe we'll finally see the long rumored but never realized 'Extreme'. Even if they wanted to do dedicated designs for the servers they'd still have had to go to Ultra style chiplets because they likely want to exceed the reticle limit for the same reason Nvidia does.

It would also allow them the option of offering a wider variety of SKUs for the Max, i.e. a "lot more CPU cores" instead of "a lot more GPU cores" if they think there's sufficient demand for that. That is if they're even willing to add SKUs to address it, since Apple has always avoided having too many choices both for manufacturing efficiency and inventory reasons, and because academic marketing research has shown again and again that too much choice makes consumers less likely to buy.

Please stick to phones.

 

[Saylick]

Not sure if serious.

I feel like the MT performance of NVL DT and Zen 6 DT will ultimately be limited by power. Intel can throw as many E cores as they want on the chip, but without drastically increasing power limits and/or making the chip that much more efficient, performance is ultimately capped by power.

 

[Josh128]

Leakfairy, we need some leaks please. This thread is starting to cannibalize itself again. 🤣

 

[adroc_thurston]

I feel like the MT performance of NVL DT and Zen 6 DT will ultimately be limited by power

Only so much 24c Z6 can do with extra wattage.
You'll get to reap the benefit of a double shrink so there's that.

 

[poke01]

I don’t get the arguments. AMD chiplet use is the most sensible and makes a ton of sense.

Base and semi- premium is monolithic

Halo is chiplet.

Apple will be copying that next year and they too will use n-1 nodes.

Intels version of chiplets is a bit too much and not smart design.

 

[OneEng2]

Big kudos to you if you actually just admit you were wrong when that time comes.

Oh, I will. I don't hang on to speculation once proof rears its ugly head .

We will get a rare opportunity to compare the cores as close to apples to apples, when both Nova Lake and Zen 6 are on N2.

I thought this as well. When have we ever been able to so easily compare architecture to architecture?

What matters is gaming performance, not Cinememe.

One could argue that neither is that important overall.

We will get to see that as well. Intel Clearwater Forest vs. Venice with Zen 5 Dense should be a good comparison, showing both in the best light.

Again, first time we have been able to clearly say approach 1 works better than approach 2 between AMD and Intel as there was always the process difference to consider. For decades, the advantage was in Intel's favor. Recently? Not so much.

No, as usual Apple shows the right way if cost isn't an issue.

Cost is always an issue when profit is a desirable outcome.

I speculate that 24C Z6 DT will be competitive with 52C NVL on e.g. compilation. With in 95±5% in Linux kernel compile w/ gcc at the same power limit.

Some rough math:

1 Zen 5 SMT core = ~ 1.5 skymont cores in MT applications that scale well.

With this ratio, it looks like Zen 6 will not keep up with NVL 52 core in this respect.

 

[Thunder 57]

I wasn't aware this was a "piss on AMD/but muh Nova Lake!" thread.

 

[CakeMonster]

Well it ships 8000 so 8000 it is.

33% bandwidth increase (I guess we'll see about latency) is quite nice at least.

The sudden increase in memory prices in the last few weeks made me wonder, but I guess lots can happen in the next 12-18 months.

 

[Saylick]

Some rough math:

1 Zen 5 SMT core = ~ 1.5 skymont cores in MT applications that scale well.

With this ratio, it looks like Zen 6 will not keep up with NVL 52 core in this respect.

On paper, it would suggest that, but that's assuming there's enough bandwidth and power to feed that many cores.

On the AMD side, I see the napkin math as follows:
Venice (N2) is a 70% uplift over Turin-D (N3E) with a 50% core count increase, so the rest (~28%) is from core-on-core uplifts alone (IPC x clocks).

Zen 6 DT gains 50% more cores and a larger node improvement (N4P to N2), so it's not hard to see a doubling of MT performance for Zen 6 DT.

 

[Kepler_L2]

On paper, it would suggest that, but that's assuming there's enough bandwidth and power to feed that many cores.

On the AMD side, I see the napkin math as follows:
Venice (N2) is a 70% uplift over Turin-D (N3E) with a 50% core count increase, so the rest (~28%) is from core-on-core uplifts alone (IPC x clocks).

Zen 6 DT gains 50% more cores and a larger node improvement (N4P to N2), so it's not hard to see a doubling of MT performance for Zen 6 DT.

33% core increase for Venice

 

[Saylick]

33% core increase for Venice

Yeah, that's my bad. Was thinking about Zen 6 DT core count increase when I was typing that. The ~28% core-on-core uplift for Venice is in-line with that 33% core count increase.

 

[Hulk]

What leaks have suggested Zen 6 will be 6+ Ghz?

 

[Saylick]

What leaks have suggested Zen 6 will be 6+ Ghz?

I present you Exhibit A: