Question Zen 6 Speculation Thread

[adroc_thurston]

Can we even consider N2P/X separate processes at all?

Kind of.

As far as I understood, one of the newer N3 chips (forgot if it was Snapdragon X2 or some Nvidia chip) uses N3P with some N3X transistors for clock-critical parts, so I'd assume this kind of mix is possible with N2P/X too and AMD would only design one 12C CCD, and not one N2P variant and one N2X variant.

yeah welcome to the world of DTCO.
And they crank CCDs with different xtor optimisations just fine.

 

[OneEng2]

Geez, sometimes the roadmap is so stupid and yet people still believe Zen6 12-core CCD will be fabbed by N2P/N2X....

View attachment 132592

Let me repeat: Venice is 32-core CCD fabbed by N2; not N2P or N2X. Meanwhile 12-core Zen6 will be fabbed by N3P/N3X. I am more inclined to believe it's N3X, same as Zen5 CCD, N4X. The rest of Zen 6 APUs and Soundwave will be fabbed by N3P. And it is aligned with TSMC's roadmap. That' why it is funny MLID speculated Zen6 will be delayed based on AMD roadmap; even though TSMC roadmap shown something more believable.

I have been speculating this for some time. It makes a great deal of sense AND it is EXACTLY how Zen 5 went.

Yup, this sounds like the classic AMD/cheapo way.

Yea, you mean the way that has made them tons of profit?

This is what Ive been postulating for a long time now and have taken insults for even suggesting it.

You and I both. I have been ridiculed severely for suggesting that AMD would do exactly what they DID DO with Zen 5 when it comes to Zen 6.

 

[adroc_thurston]

It makes a great deal of sense AND it is EXACTLY how Zen 5 went.

znver5 was all N3.

I have been ridiculed severely for suggesting that AMD would do exactly what they DID DO with Zen 5 when it comes to Zen 6.

Zen5 was N3.
It was only backported because N3b was not showing major signs of life for a while.

 

[branch_suggestion]

I have been speculating this for some time. It makes a great deal of sense AND it is EXACTLY how Zen 5 went.

Because N3B sucked, N4P was the backup option.

Yea, you mean the way that has made them tons of profit?

They ain't going for the poors anymore, best node is the priority except for mainstream stuff and big GPU dies are too risky for N2 at this time.

You and I both. I have been ridiculed severely for suggesting that AMD would do exactly what they DID DO with Zen 5 when it comes to Zen 6.

Everybody is using N2 for their CPUs in late 2026/2027, AMD would be at a noticeable disadvantage if they didn't use N2 for their premium parts.
They ain't broke no more, gotta use the best to be the best and that is pretty clearly what they strive to be.

 

[OneEng2]

Everybody is using N2 for their CPUs in late 2026/2027, AMD would be at a noticeable disadvantage if they didn't use N2 for their premium parts.
They ain't broke no more, gotta use the best to be the best and that is pretty clearly what they strive to be.

Zen 5 is on N4P and it does a pretty good job of handling ARL on N3B... at much less cost.

 

[adroc_thurston]

Zen 5 is on N4P and it does a pretty good job of handling ARL on N3B... at much less cost.

AMD has bigger fishes to compete with.

 

[Joe NYC]

AMD has bigger fishes to compete with.

Such as holding back the Arm hordes...

 

[adroc_thurston]

Such as holding back the Arm hordes...

It's not a horde, Apple's the only non-lobotomized player in the market.
But Intel's just not gonna be competitive till UC.

 

[Joe NYC]

It's not a horde, Apple's the only non-lobotomized player in the market.
But Intel's just not gonna be competitive till UC.

I think the ultimate challenge in datacenter is for AMD to demonstrate superior TCO over AWS Gravitron (including R&D resources required).

 

[Josh128]

znver5 was all N3.

Zen5 was N3.
It was only backported because N3b was not showing major signs of life for a while.

Yet Arrow Lake was launched only 2 months later than Zen 5...on N3. That makes no sense.

 

[Thibsie]

Yet Arrow Lake was launched only 2 months later than Zen 5...on N3. That makes no sense.

If Intel had already signed the contract for wafers, of course it does.
AMD was careful, Intel been idiot AFAICT.

 

[adroc_thurston]

I think the ultimate challenge in datacenter is for AMD to demonstrate superior TCO over AWS Gravitron (including R&D resources required).

Kind of.
ARM TCO hinges on ARM itself eating poopoo margins which is not forever.

Yet Arrow Lake was launched only 2 months later than Zen 5...on N3. That makes no sense.

Doesn't matter, AMD did not consider N3 an alive node to commit to it fully.

 

[yuri69]

Everybody is using N2 for their CPUs in late 2026/2027, AMD would be at a noticeable disadvantage if they didn't use N2 for their premium parts.
They ain't broke no more, gotta use the best to be the best and that is pretty clearly what they strive to be.

Sure, their 32c CCD-based products are premium parts. The same goes for the MI400-series. The rest of the stack is not so clear.

AMD wasn't really broke at the time they designed Zen 4... Now we are talking about the Zen 6 launch.

 

[adroc_thurston]

The rest of the stack is not so clear.

Very premium unless you think SP8 Venice is for the poors.

 

[Joe NYC]

Kind of.
ARM TCO hinges on ARM itself eating poopoo margins which is not forever.

Good point. Arm provides half of the R&D, gives it away at low margins. I wonder if / when Atm changes these terms since Arm wants the server market for itself, for its own merchant silicon.

 

[Joe NYC]

Sure, their 32c CCD-based products are premium parts. The same goes for the MI400-series. The rest of the stack is not so clear.

Server chips using 12 core CCDs will offer very high end single thread performance in server environment, so also a premium product.

Client product using the 12 core CCD will also be for premium segments for client market.

AMD wasn't really broke at the time they designed Zen 4... Now we are talking about the Zen 6 launch.

N5 was a fine node for Zen 4, N2P will be leading edge node without any doubt.

If Zen 5 was launching in 2025, it would definitely have used N3P, but the other N3 nodes before N3P were not a good fit for AMD