Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[StefanR5R]

Die to die connection changes require a new die.

No, they do not. They just require that the CCD features both interfaces. Same as MI300A, same as X3D, they all use the same CCDs as the vanilla products.

Its a new low power core option.

No. GMI is uncore.

I still maintain that the roadmap is referring to the Strix Halo cores, as they are not C cores, yet can operate at much lower power than standard cores.

Per-core power is "low" in several Turin SKUs as well.

 

[StefanR5R]

they all use the same CCDs as the vanilla products.

PS: Different bins though, and possibly different steppings.

 

[CouncilorIrissa]

We're talking about AMD here. They're the last company in the industry to tape out another core design for the product lineup that's going to appear in 10 low-volume SKUs at most, on client no less.
It would be extremely uncharacteristic of them.

 

[adroc_thurston]

No way this is N2P/x those are entering HVM in 2026

Yeah times perfectly.

Wont be N2 unless its still 3 years out. N3P is possible, but so is N3E. Either way, max frequencies arent going up, and it will bring a ~10% IPC uplift

Just don't.

 

[511]

Yeah times perfectly.

Bruhhhhh you don't understand the time HVM entering in H2 26 means products launch Q2 27 at the earliest Zen6 is H2 26 launch

 

[Kryohi]

We're talking about AMD here. They're the last company in the industry to tape out another core design for the product lineup that's going to appear in 10 low-volume SKUs at most, on client no less.
It would be extremely uncharacteristic of them.

I kinda agree, but at the same time we have to consider the current AMD is very different from the AMD that developed zen 1 to zen 4. Around the time they started working on Halo, they had probably realized they weren't a broke company without profits anymore, and their products were going to beat Intel ones for a long time.
They finally had room for a few risky projects without immediate returns.

 

[adroc_thurston]

they all use the same CCDs as the vanilla products.

loud incorrect buzzer noise
WRONG. Desktop and server do not share the CCD, just the design itself.

Bruhhhhh you don't understand the time HVM entering in H2 26 means products launch Q2 27 at the earliest Zen6 is H2 26 launch

N2 got pulled in. Next.

 

[Josh128]

No, they do not. They just require that the CCD features both interfaces. Same as MI300A, same as X3D, they all use the same CCDs as the vanilla products.

No, Halo has unique CCDs.

 

[StefanR5R]

Desktop and server do not share the CCD, just the design itself.

More differences than just another stepping?

 

[MarutTheSlayer]

These fantasies that non-portable computers will eventually be replaced by portable ones are complete nonsense.
– Ergonomics,
– potential computing capacity,
– economics
of portable computers are drastically inferior to non-portable ones.

But non-portable computers will be mostly relegated to workstations, either compact desktops, or HEDT like, and DIY gaming enthusiasts.
A high-end laptop with 35-45W TDP for CPU & iGPU, and a dGPU that gets active for serious engineering or gaming, can already do more than a high end desktop from just 5 years ago.
The next step is the same performance coming to more thinner designs for a premium while the more Pro laptops get more power with M4 Max like computers. Nvidia will also introduce one surely as they bring ARM SoCs.

 

[adroc_thurston]

More differences than just another stepping?

Yeah, very very different xtor-level optimizations.

 

[dr1337]

If its just a different GMI interconnect, why isn't there a chance its already on all the normal CCDs? It could have a legacy mode for the old desktop IO die, and the new mode for higher spec controllers.

I honestly don't believe the rumors, or, if they did make a new die just for strix halo, then that guarantees a Zen 5+ release at some point. Literally they would have been better off making strix halo monolithic if the CCDs aren't being used anywhere else. Makes zero sense. Also a lot of money to waste on extra validation, extra silicon and substate operations, ect.

If anything we can interpret the statement as regarding the physical connections. I.E. instead of being on a normal PCB type substrate like the current desktop chips, strix halo is simply using some kind of MCM/silicon interposer to facilitate the GMI links. That is afterall, how they "connect the two dies" and the CCDs being right against the IOD directly implies advanced packaging.

 

[Thibsie]

I honestly don't believe the rumors, or, if they did make a new die just for strix halo, then that guarantees a Zen 5+ release at some point. Literally they would have been better off making strix halo monolithic if the CCDs aren't being used anywhere else. Makes zero sense. Also a lot of money to waste on extra validation, extra silicon and substate operations, ect.

Nope, just a test véhicule for Zen6.
This just makes a lot of sense. Low risk, test feasibility.

 

[Doug S]

Absolutely nobody have said anything about scaling Andoid Apps to Windows.

I was talking, for very reasons you mentioned, about scaling Android OS to desktop and laptop form factors.

Vertical integration of Android ecosystem with ARM chips becomes absolutely possible now.

What's the point? It would replace ChromeOS as the low end cheap crap for school kids option. It would never have a chance in hell of competing with Windows.

 

[MS_AT]

If its just a different GMI interconnect, why isn't there a chance its already on all the normal CCDs? It could have a legacy mode for the old desktop IO die, and the new mode for higher spec controllers.

My uninformed guess, would be that they are using "sea of wires" for a reason and that reason is they have changed from "more serial" physical interconnect clocked at 20sth GHz to a "more parallel" one they can clock at 2 GHz. Since they maintain BW, that means they have ~roughly 10 times more wires, meaning more contacts on the CCD itself. Since IO takes space might be they have done some frequency space trade-off on rest of the chip to accommodate more IO and keep sensible v/f curve, since Halo is limited to 5.1GHz boost.

But yea, it's just a guess, maybe somebody can correct me if I missed the picture

 

[fastandfurious6]

500 pages of speculation taught me CPU companies are significantly impacted by long manufactur process, very tight timelines and TSMC timeslots and even tighter competitive schedules bc rivals

and always the failures we never learn about

strix point was gutted bc it had to catch up "copilot" BS

zen 5 also 'rushed', even delayed some weeks to fix bugs last moment

probably also partly gutted

they have to use existing parts to speed up the process

x3d limited parts bc limited manufactur capacity

Halo they could wait a bit so bit by bit they put on new stuff to reuse for zen6 ++

and so on

 

[fastandfurious6]

man this cutthroat competitiveness is bad for everyone

I want 10+ years coasting with bulldozer again... performance sucked but the world was much better 🌞

Bulldozer Aryzen 👌

 

[Hitman928]

AMD says a special edition 9950x3d with both CCDs having Vcache might come to be, but not likely.

We could make a Ryzen 9 9950X3D with 3D V-cache on all 16 cores, AMD tells us

AMD confirms that it could make a limited edition dual-CCD Ryzen X3D gaming CPU with 3D V-cache on both CCDs, but it would be a niche product.

www.pcgamesn.com

 

[Thunder 57]

AMD says a special edition 9950x3d with both CCDs having Vcache might come to be, but not likely.

We could make a Ryzen 9 9950X3D with 3D V-cache on all 16 cores, AMD tells us

AMD confirms that it could make a limited edition dual-CCD Ryzen X3D gaming CPU with 3D V-cache on both CCDs, but it would be a niche product.

www.pcgamesn.com

Not surprising. Surely AMD has samples and knows the numbers. I don't know why there are armchair CPU designers out there who think they know better.

 

[DrMrLordX]

Not surprising. Surely AMD has samples and knows the numbers. I don't know why there are armchair CPU designers out there who think they know better.

It would calm some people's OCD.

 

[511]

It would calm some people's OCD.

Obessive CCX Disorder?

 

[coercitiv]

Obessive CCX Disorder?

Obsessive Cache Disorder

 

[yuri69]

Not surprising. Surely AMD has samples and knows the numbers. I don't know why there are armchair CPU designers out there who think they know better.

Well, it is surprising. What is the investment needed for introducing such dual-CCD SKU? What else on top of proper binning and producing a fw revision is required?

Back in the days, AMD was not afraid of having halo CPU products - the original AMD 64 FX line, hilarious Quad-FX line, Black Edition even with TWKR mini-edition, etc. Releasing a dual-CCD halo named "Ryzen Gaming Max Xtreme FPS X3D Ultra" would be easy since it would bring a few 1st places more than the single-CCD SKU...

 

[LightningZ71]

I think it would be more likely that it's released under the Epyc 4xxx line...

 

[igor_kavinski]

Well, it is surprising. What is the investment needed for introducing such dual-CCD SKU? What else on top of proper binning and producing a fw revision is required?

I think it's more of a "mental" issue than a technical one in greenlighting the dual CCD SKU for production. The person deciding that (maybe Lisa) probably thinks like so:

1 V-cache die == 1 Halo SKU == PROFIT

2 V-cache dies == 1 Halo SKU == 1.25 x PROFIT == Loss of 0.75X in PROFIT == Not worth taking blame for in times of financial distress

2 V-cache dies == 1 Halo SKU == 2 x PROFIT == Angry people == Not worth the bad PR

That last one, we need to unite, pool our financial resources and present AMD with upfront funds to get these special CPUs made to order.