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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Only 43 days left until the AMD keynote at Computex on June 3 and still not any solid leak. I wonder if we’ll get any credible and precise performance numbers or pricing info before that, or if AMD will manage too keep everything secret until we hear it from Lisa Su directly. Any opinions, based on e.g. past track record?
We need to wait for more compatile BIOS releases. So far there was just a single one.
 
We need to wait for more compatile BIOS releases. So far there was just a single one.
Both ASUS and MSI have released BIOS for Zen5:


Quite recently though (as in just a few days ago). So maybe Zen5 CPU performance leaks can be expected to follow soon?
 
Board compatibility engineering/ qualification on AM5 should be rather straightforward (if the cIOD hasn't changed, as rumored). Therefore I guess that there is a possibility that there are still no CPUs outside AMD yet with which these BIOSes are compatible.
 
Your guys should take another hint: Someone is MIA...
Yep, I noticed this also. And I thought exactly the same.
Given where he purports to live, I hope your use of military jargon is coincidental...

It's not like he's the only source of Zen5 being OP...
Well he is active on Twitter/X. Also most of them have the same source, I think it's a Discord where they all are in and sometimes someone posts some results.

If I remember correctly, their "ZEN 5 April Launch" stuff was information from November last year, and they still said it was true, after some different rumors emerged in January, before AMD themselves said H2 at end of January.

However it's still not his style to say nothing about it, even if he is dead wrong he will just igbore it and start hyping the next thing from AMD. He did the same with RDNA3 after all.
 
Yep, I noticed this also. And I thought exactly the same.

Well he is active on Twitter/X. Also most of them have the same source, I think it's a Discord where they all are in and sometimes someone posts some results.

If I remember correctly, their "ZEN 5 April Launch" stuff was information from November last year, and they still said it was true, after some different rumors emerged in January, before AMD themselves said H2 at end of January.

However it's still not his style to say nothing about it, even if he is dead wrong he will just igbore it and start hyping the next thing from AMD. He did the same with RDNA3 after all.
Still yet to see one convincing argument that the core isn't 40 points of IPC. Amd did multiple 20ish cores that are all fundamentally the same size and a core that is massively bigger gets what?

People are literally betting on worse then bulldozer execution. Bulldozer cores were significantly narrower then k10 and had a horrible cache implementation and achieved about the same IPC.

They are going from a skylakish sized core to a gc sized core , justify why amds execution will be worse then Intel's.....
 
However it's still not his style to say nothing about it, even if he is dead wrong he will just igbore it and start hyping the next thing from AMD. He did the same with RDNA3 after all.
Well, let's agree the last few pages of this thread haven't been that interesting, when we got invaded by the Intel threaders and their copium, and we ended up talking about zen4 again, for some reason...

Hopefully new leaks from now on will reinvigorate the conversation.
 
They are going from a skylakish sized core to a gc sized core
Not quite.
Well he is active on Twitter/X.
if by that you mean "retweeting every picture of Kazusa there is", yeah.
crikey, I have stalkers now.
If I remember correctly, their "ZEN 5 April Launch" stuff was information from November last year
that was the mobo vendor timeline and it slipped.
Also most of them have the same source
not really, no.
However it's still not his style to say nothing about it, even if he is dead wrong he will just igbore it and start hyping the next thing from AMD. He did the same with RDNA3 after all.
Well thing is, I'm not wrong about RDNA3.
6 weeks left!
 
Hehe, I wouldn't say no to the 3D, but I'm not gonna wait for it, and its blissful to avoid worrying about the scheduling between freq/cache CCX's if they keep that layout.
 
Still yet to see one convincing argument that the core isn't 40 points of IPC. Amd did multiple 20ish cores that are all fundamentally the same size and a core that is massively bigger gets what?

People are literally betting on worse then bulldozer execution. Bulldozer cores were significantly narrower then k10 and had a horrible cache implementation and achieved about the same IPC.

They are going from a skylakish sized core to a gc sized core , justify why amds execution will be worse then Intel's.....
From generation to generation, Zen was larger in terms of the logic used and the number of transistors used for it. Zen 3 compared to Zen 2 is generally a redesign of the control logic and the algorithms contained in it, and an expansion of about 14%. This proves that the logic in Zen 2 was not designed optimally for the amount of resources.
 
From generation to generation, Zen was larger in terms of the logic used and the number of transistors used for it. Zen 3 compared to Zen 2 is generally a redesign of the control logic and the algorithms contained in it, and an expansion of about 14%. This proves that the logic in Zen 2 was not designed optimally for the amount of resources.

Let s say that it was somewhat rushed, but so was Zen since Zen+ had 5% better MT IPC without almost nothing being changed.
 
Let s say that it was somewhat rushed, but so was Zen since Zen+ had 5% better MT IPC without almost nothing being changed.
Zen 1+ consists mainly of fixes, among others, in the microcode. Zen1+ fixed what Zen1 couldn't do in time.
 
The whole point of derived cores is iteratively bigger designs
The key to microarchitecture is the control logic and the algorithms it contains. This part is a closely guarded secret.

Yes, it is not the number of units or the size of buffers but the logic managing them that is the key to optimal use of resources.

For this reason, with the same amount of ALU and decoding width, Zen 3 brought an average of +19% higher IPC. The entire control logic has been replaced with a redesigned and expanded one.
 
The key to microarchitecture is the control logic and the algorithms it contains.
Wha.
Yes, it is not the number of units or the size of buffers but the logic managing them that is the key to optimal use of resources.
What.
The entire control logic has been replaced with a redesigned and expanded one.
Zen3 literally piled on the port count.
There's a ton more EUs, just more specialized ones.
 
Yes, it is not the number of units or the size of buffers but the logic managing them that is the key to optimal use of resources.

For this reason, with the same amount of ALU and decoding width, Zen 3 brought an average of +19% higher IPC
What did I just read...? )
 
Do we have an idea of how RAM will work in Strix Halo? Fully unified, as in a Mac? Or with a part of it reserved for the GPU, as in integrated graphics solutions?

I'm interested in the part for IA RAM heavy workloads, but that would only be a differentiator under the Mac fully unified model. If a portion of RAM is to be reserved, then I could go for a laptop with an Nvidia GPU - since Strix Halo wouldn't have the advantage of a huge pool of RAM vs a GeForce card.

Edit: like the only way to run Llama 3 70B is with an M2/3 Max with at least 64 GB, and from what I see on Twitter even that's rather short on RAM.
 
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