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C
carancho
Junior Member
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Feb 24, 2013
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Today at 3:48 PM
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C
carancho
reacted to
DisEnchantment's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
No, it means Charlie is deranged.
Today at 3:44 PM
C
carancho
reacted to
coercitiv's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
Pepper the slide with cut-down variants while talking about multiple sources Ensure there's enough ambiguity to cover all kinds of...
Today at 7:32 AM
C
carancho
reacted to
uzzi38's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
Frankly, the existence of the 128-bit "LP" model there puts this whole slide under doubt. That one doesn't make any sense in the...
Today at 7:31 AM
C
carancho
reacted to
Nothingness's post
in the thread
Discussion
Qualcomm Snapdragon Thread
with
Like
.
That can be quite complex: uops are stored in queues between decoder and dispatch; also a decoder could emit two uops per cycle. For...
Yesterday at 10:34 PM
C
carancho
reacted to
Aapje's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Haha
.
Must be a very strix embargo. ...sorry.
Yesterday at 10:30 PM
C
carancho
reacted to
Doug S's post
in the thread
Discussion
Apple Silicon SoC thread
with
Like
.
There is unlikely to be that much interdie variation, certainly not at the level Apple is binning. Apple's speed binning is pretty lax...
Yesterday at 10:21 PM
C
carancho
reacted to
Doug S's post
in the thread
Discussion
Apple Silicon SoC thread
with
Like
.
Yeah the node that made binning complex for Apple was N3B because it is so bad. N3E is back to normal TSMC yields, where Apple's "bin on...
Yesterday at 10:19 PM
C
carancho
reacted to
Mopetar's post
in the thread
Discussion
Apple Silicon SoC thread
with
Like
.
That's my point. N3E had better yields, hence Apple has no reason to sell you an iPad with only 3 performance cores when the amount of...
Yesterday at 10:17 PM
C
carancho
reacted to
Doug S's post
in the thread
Discussion
Apple Silicon SoC thread
with
Like
.
Based on the 'best' scores in GB6 ST Apple gained about 15% from M2 to M3. Apple E cores tend to be worth about 1/3 of a P core, so an 8...
Yesterday at 10:15 PM
C
carancho
reacted to
Mopetar's post
in the thread
Discussion
Apple Silicon SoC thread
with
Like
.
It's not the node that does it, but more aggressive binning. Yields are not so bad that Apple has to disable a performance core for the...
Yesterday at 10:13 PM
C
carancho
reacted to
Ranulf's post
in the thread
Intel processors crashing Unreal engine games (and others)
with
Haha
.
Must be fresh fin-fet chirpin season out there in the sweltering sweatlands known as Meteor Lake. Nowadays no one remembers the lowest...
Yesterday at 2:17 PM
C
carancho
reacted to
adroc_thurston's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
LNL is more purpose-built for that. That's all there is to it.
Monday at 10:19 PM
C
carancho
reacted to
adroc_thurston's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
This.
Monday at 10:19 PM
C
carancho
reacted to
Abwx's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
It will, next year when Strix Halo land everything will be haloed.
Monday at 10:19 PM
C
carancho
reacted to
adroc_thurston's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
Congrats on pissing OEMs off.
Monday at 10:18 PM
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