Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Insert_Nickname]

When Mark turns all his computers on, the lights in the neighborhood dim

Sorry, couldn't resist...

 

[BorisTheBlade82]

The genoa 4 CCD devices don't make too much sense, or at least, it doesn't seem to make that much sense for them to have dual GMI links. They are relatively low clocked parts, but they do have 6 to 8 cores, so it is unclear whether they can actually consume that much bandwidth. If they took an 8 CCD F-series part and connected them with dual GMI links, then that seems to make more sense, although they are lower core count per CCD and higher cache per core.

If they do have 16 GMI links then why aren't they available now? Are current IO die salvage parts with disabled links? Will there be a new version of the IO die instead? They are a relatively large chip on 6 nm, so having defective parts may be more likely than 14 nm IO die.

You seem to be confusing something:
The current sIOD only has 12 IFoP ports, that is why they can only use narrow mode for the Top end SKUs.
As the IFoP only supplies 64/32 GByte/s/Port, you need wide mode on the low CCD count SKUs in order to be able to make use of those pretty 12 channels of RAM.
And 4 CCD SKU means up to 32 cores, not 6 to 8. To my knowledge, ALL server SKUs <=4 CCD use wide mode - the F-series ones as well.

 

[A///]

haven't seen those old units in years. they went all digital faceplates in the 2000s.

 

[Timmah!]

Yup it's Styx.

your heart is human, your blood is boiling, your brain I.B.M.?

 

[jamescox]

You seem to be confusing something:
The current sIOD only has 12 IFoP ports, that is why they can only use narrow mode for the Top end SKUs.
As the IFoP only supplies 64/32 GByte/s/Port, you need wide mode on the low CCD count SKUs in order to be able to make use of those pretty 12 channels of RAM.
And 4 CCD SKU means up to 32 cores, not 6 to 8. To my knowledge, ALL server SKUs <=4 CCD use wide mode - the F-series ones as well.

Edited a bit for clarity and readability.

No, I am not confusing anything. The post somewhere above seemed to imply 16 cpu chiplet parts, which would mean they would need 4 ports per quadrant, 16 total. I was refering to 6 to 8 cores per CCD for the 4 CCD devices. They are at rather low clock, so it is unclear how much of a difference wide mode will make.

The genoa F-series parts are all 8 CCD at 2, 3, 4, or 6 cores per CCD, but if it only has 12 ports, then they cannot be in wide mode. If they use the same IO die for Zen 5, then it may make some sense that the IO die design actually has 16 ports for future use. That is why I was wondering if current IO die parts are salvaged to some extent.

Perhaps they are stockpiling fully functional IO die for a future release. It would make some sense for the 6 nm IO die to be more likely to have defects than the old 14 nm IO die. I don't know if they will be using salvage IO die for the SP6 part also. Those could have non-funtional pci-express and memory controllers if a salvage part is used. I expected a different, smaller IO die for SP6 given the likely volume, but who knows.

 

[BorisTheBlade82]

No, I am not confusing anything. The post somewhere above seemed to imply 16 cpu chiplet parts, which would mean they would need 4 ports per quadrant, 16 total. I was refering to 6 to 8 cores per CCD for the 4 CCD devices, but at rather low clock, so it is unclear how much of a difference wide mode will make. The genoa f-series parts are all 8 CCD at 2, 3, 4, or 6 cores per CCD, but if it only has 12 ports, then they cannot be in wide mode. If they use the same IO die for Zen 5, then it may make some sense that the IO die design actually has 16 ports for future use. That is why I was wondering if current IO die parts are salvaged to some extent. Perhaps they are stockpiling fully functional IO die for a future release. It would make some sense for the 6 nm IO die to be more likely to have defects than the old 14 nm IO die. I don't know if they will be using salvage IO die for the SP6 part also, except those may have non-funtional pci-express and memory controllers. I expected a cut down IO die for SP6 given the volume, but who knows.

Locuza already provided an annotated die shot which proved 12 ports - no harvesting.

https://twitter.com/x/status/1592489135880953858

 

[moinmoin]

Adroc, allow me to move this discussion here.

Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.

I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.

 

[Exist50]

Adroc, allow me to move this discussion here.

I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.

Nah, on that, at least, he's right. Zen 3 is really its thing. At least from a core perspective.

 

[moinmoin]

Nah, on that, at least, he's right. Zen 3 is really its thing. At least from a core perspective.

Yeah, the core perspective. That's what it's amounts to which is my point and my expectation for the major difference between Zen 3 and 5, the latter not being limited to just that.

 

[Exist50]

Yeah, the core perspective. That's what it's amounts to which is my point and my expectation for the major difference between Zen 3 and 5, the latter not being limited to just that.

I would be surprised if AM5 really had any impact either way. The core design point is unlikely to be dictated by the desktop socket. They will probably take better advantage of the power headroom, but they also probably wanted Zen 5 on N3, so...

I think Zen 5 will be quite a good core. Just not the second coming of Zen. I thought some recently leaks were starting to cool the hype train somewhat.

 

[adroc_thurston]

Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens.

So is Zen5.

but they also probably wanted Zen 5 on N3

Yea, which is like the reason it's as ambitious as it is.

I think Zen 5 will be quite a good core

Literally the best in the entire industry.

Just not the second coming of Zen

It is.
Apple-class cores don't grow on trees.

I thought some recently leaks were starting to cool the hype train somewhat.

What leaks?

 

[Exist50]

What leaks?

I forget the specifics, but IPC more in the 20% ballpark. Probably in this thread somewhere.

 

[adroc_thurston]

but IPC more in the 20% ballpark

That's just comical.
Zen3 got there and it was tiny.
Zen5 is not tiny, not at all.

 

[Exist50]

Zen5 is not tiny, not at all.

So were Sunny Cove and Golden Cove. Need more than raw size to judge IPC.

 

[adroc_thurston]

So were Sunny Cove and Golden Cove

Yea but IDC sucks at making good big cores.

Need more than raw size to judge IPC.

Yea, for that you have a Turin 96c part.
Very simple, really.

 

[moinmoin]

So is Zen5.

Wait, so does Zen 5 still use the same Zen 2 style IOD setup with the at this point heavily bottlenecking CCX links? I thought this was just due Zen 4 being a direct evolution of Zen 3 which reused the IOD of Zen 2 that this carried over to AM5.

 

[adroc_thurston]

Wait, so does Zen 5 still use the same Zen 2 style IOD setup with the at this point heavily bottlenecking CCX links?

Yea.
Genoa era c/sIOD's are very very different from Zen2/3 ones anyway.

which reused the IOD of Zen 2 that this carried over to AM5

It absolutely, most definitely did not.
The fabric topology is completely different.

 

[moinmoin]

The fabric topology is completely different.

The link speed however is still the same.

 

[adroc_thurston]

The link speed however is still the same.

Eh, twice the speed, half the width.
And it is faster overall.

 

[DisEnchantment]

Literally the best in the entire industry

Zen5 is not tiny, not at all.

Do you want to provide background context, quantifiable information even if with caveats/disclaimer, etc. It is quite difficult to have a 'discussion' with only superlative adjectives. Or we can stick to mundane boring discussion without the assertive statements if you don't wish to share stuff. Lots of folks know actual things, but if professional obligations gets in the way we keep our mouth shut and play along ignorant.
It is fine if you don't want to but since the pages are rolling with barely any new information I just want to ask.

 

[adroc_thurston]

Do you want to provide background context

Again, it's an Apple-class core.
That's really what you need to know.
Very simple.

 

[moinmoin]

Eh, twice the speed, half the width.
And it is faster overall.

Zen 3 CCDs have 32B/cycle read/write speed. Zen 4 CCDs have 32B/cycle read and 16B/cycle write speed. Do I fail at reading following slides correctly?

 

[adroc_thurston]

Zen 3 CCDs has 32B/cycle read/write speed

It was also half the write speed (so 16B), so <8 CCD configs always had reduced DRAM write b/w on Rome/Milan.
Same rules apply to Genoa/Turin, just that the links themselves clock faster (relatively) and there's more of them.

Oh yea USRs on Navi31/32 are also half the write bandwidth relative to reads.
AMD loves doing this trick to save on active link power it seems.

 

[moinmoin]

It was also half the write speed (so 16B), so <8 CCD configs always had reduced DRAM write b/w on Rome/Milan.
Same rules apply to Genoa/Turin, just that the links themselves clock faster (relatively) and there's more of them.

So no change. And no change in Zen 5 as well?
Contrast that to Apple's approach where a single core can saturate all of the memory bandwidth. (Not that that would be a good idea with massive multicore chips lol.)

 

[adroc_thurston]

And no change in Zen 5 as well?

No.

Contrast that to Apple's approach where a single core can saturate all of the memory bandwidth.

That's a fabric design choice more or less, not like the core really needs it (see very much-much decent MT scaling on Apple chips).