Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Ajay

Lifer
Jan 8, 2001
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jpiniero said:
OMG Reverse Hyperthreading!
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Not really. If in fact AMD is going wider on the front end like Apple, then there should be a greater extraction of ILP (instruction level parallelism). This would make hyperthreading yields lower - and possibly not worth the extra silicon for SMT anymore. JITs could improve ILP on the fly if updated or recompilation with improved compilers for machine coded executables.
 
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HurleyBird

Platinum Member
Apr 22, 2003
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Ajay said:
Not really. If in fact AMD is going wider on the front end like Apple, then there should be a greater extraction of ILP (instruction level parallelism). This would make hyperthreading yields lower - and possibly not worth the extra silicon for SMT anymore. JITs could improve ILP on the fly if updated or recompilation with improved compilers for machine coded executables.
Click to expand...

Well, this is going to depend a lot on implementation details, but you got that generally backwards. Increased ILP will not scale anywhere near 1:1 as you add more resources to the core. Everything else being equal, when you have more resources sitting idle more often, that is beneficial for SMT.
 
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uzzi38

uzzi38

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Oct 16, 2019
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@Kepler_L2 You're jumping the gun a little.

Lets just take a look again at what we're talking about here. The document shows us a new feature that lets you poll a core to check how many SMT threads a single individual core supports. Why would you want to ever poll a single core individually? Start from there.
 
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Geddagod

Golden Member
Dec 28, 2021
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Thibsie said:
What project ?
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soft machines version of core fusion. IIRC the cores were able to be pretty tightly knit- as in a couple cycles worth of latency, able to act as one giant core or multiple smaller, less wide cores, but it also had to have a software translation layer. There's an anandtech article if you care to read more about it.
Maybe Intel is working on a similar project on the background, who knows, but Cutress said the project was mothballed and the personal from the original acquisition had since dispersed, possibly due to frequency issues of the design. Read somewhere (forgot where, so if it was here, I'm sorry that I'm not quoting whoever lol) that Intel is pathfinding ~1 or 2 'next gen' architectures at the same time, so VISC fusion cores might have been one of those projects at some point.
 
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Exist50

Platinum Member
Aug 18, 2016
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Kepler_L2 said:
Zen6 stuff. Not in any publicly leaked roadmap yet :p
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You tease :). Can you at least tell us what "SX" is? Styx, if I had to guess.
uzzi38 said:
Lets just take a look again at what we're talking about here. The document shows us a new feature that lets you poll a core to check how many SMT threads a single individual core supports. Why would you want to ever poll a single core individually? Start from there.
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uzzi, are you implying that they are adding a feature to disable SMT on a per core basis? Do they not have that already?
 
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uzzi38

uzzi38

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Exist50 said:
You tease :). Can you at least tell us what "SX" is? Styx, if I had to guess.

uzzi, are you implying that they are adding a feature to disable SMT on a per core basis? Do they not have that already
Click to expand...

I don't know the codename so I couldn't tell you anyway, even if I wanted to.

And no, that's not what I'm saying. I'll be honest, I can't think of a way of implying it without saying it outright, so I'm going to shut up now.
 
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soresu

Diamond Member
Dec 19, 2014
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Exist50 said:
Can you at least tell us what "SX" is? Styx, if I had to guess
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Did you mean Strix/Strix Point?

Pretty sure I've already seen that listed as STX - seems unlikely that they would name something so close to a previous product codename.

Edit: Missed Kepler's post, just ignore this.
 
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Tuna-Fish

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Mar 4, 2011
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Exist50 said:
uzzi, are you implying that they are adding a feature to disable SMT on a per core basis? Do they not have that already?
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This is not about disabling HT through software, it's about asking if the core is capable of HT in the first place.

And the reason is probably making scheduling easier. Right now, on Intel the small core/big core divide is not as much of a problem as it could be for scheduling because a small core is pretty close in performance to one HT thread of the big core. That is, if all threads on the CPU are loaded, they are all about equally fast. The problem cases where it's difficult for schedulers is when the available parallelism of multithreaded workload is > the amount of big cores, but not unbounded.

When AMD ships c and normal cores as part of a single CPU, this is not true for them. If both cores have SMT2, when every core is loaded, the c cores have significantly lower throughput, assuming they clock significantly lower. If SMT2 is disabled for them, this would be fixed, and in the client world where the windows scheduler determines how good your product is, it might be worthwhile to match what Intel does so that the systems work the same.
 
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