Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[gdansk]

[This has been discussed to death by now, but: A) What has been semi-valid for Zen 4 is no longer going to be valid for Zen 5. B) They are "better off" only in a fantasy world in which operating systems have an omniscient task scheduler. In the real world, heterogeneous CPUs are in some economic respects preferable to homogeneous CPUs, but from the technical perspective they are nothing but kludges.]

The complete current wording of the mantra is "go buy EPYC, but not EPYC 4000". Earlier versions of the mantra also mentioned a "Threadripper" but this was a long time ago.

Even the plain old 9950X is dependent on preferred CCD scheduling for peak performance. We all lament that but it is the real world for months now.
EPYC 4004 doesn't have any dual cache CCD parts but its successor stands the best chance (after sales channels are saturated with 9800X3D). Threadripper is not being refreshed frequently because self-identified workstation enthusiasts aren't a big market and most prefer used EYPC instead.

 

[LightningZ71]

There is one answer to this, and as a former scalper myself (sorry, PS3 launch), I can confidently declare--- NEVER pay above MSRP for tech. F***k 'em, dont do it. A little self control will put a world of hurt on scalpers. They can keep their stock until AMD restocks, and restocks again until I get MSRP or better. This is the way.

There are enough people out there that don't have a practical limit on what they will spend on new hotness without caring about the risks that will forever give scalpers a target market.

 

[Kepler_L2]

Even the plain old 9950X is dependent on preferred CCD scheduling for peak performance.

Actually since OS schedulers tend to go from highest frequency to lowest in priority, and CCD1 cores all have lower frequency than CCD0, a "CCX-unaware" scheduler should still work just fine.

 

[gdansk]

Actually since OS schedulers tend to go from highest frequency to lowest in priority, and CCD1 cores all have lower frequency than CCD0, a "CCX-unaware" scheduler should still work just fine.

The reviewer guide gave steps to avoid bad scheduling because Windows 11 was too clever for that.

But yes us noble linux users (top 2% really) were always fine.

 

[aigomorla]

Cliff's :

Cpu melted socket..,.
Its not related to EXPO so don't freak out.
CPU socket was shown somehow the cpu shifted .1mm alligning the ground with the VCC causing a major short.

In short... MAKE SURE YOU PERFECTLY SEAT THAT CPU.

 

[StefanR5R]

[…] they can't charge too much for EPYC 4000 since it's just rebadged "consumer" stuff, Intel solved this problem in the past by removing support for ECC, but since Zen 4/5 support it (if you get BIOS and mb) it's hard for AMD to do that.

AMD currently perform the same segmentation with Ryzen 8000G vs. Ryzen PRO 8000G: Phoenix's and Phoenix 2's IMC supports ECC, but the non-PRO SKUs have it disabled AFAIK. Likewise, Ryzen 4000G vs. Ryzen PRO 4000G alias Renoir.

Edit,

EPYC 4004 doesn't have any dual cache CCD parts but its successor stands the best chance […]

I agree but add that "best" doesn't imply "good".

[…] (after sales channels are saturated with 9800X3D).

Well, EPYC 4004 appeared two years after Ryzen 7000, and 1½ years after Ryzen 7000X3D. I am guessing AMD aren't quite in a hurry to release EPYC 4005 either.

 

[Win2012R2]

I am guessing AMD aren't quite in a hurry to release EPYC 4005 either.

Incompetence - they could have made extra couple of hundred bucks for the same 9000 series product, more if they had both chiplets with 3D cache, free money.

 

[adroc_thurston]

Incompetence

Lmao

they could have made extra couple of hundred bucks for the same 9000 series product, more if they had both chiplets with 3D cache, free money.

These things are niche to begin with, and V$ parts moreso. Get real.

 

[dr1337]

I really don't know why anyone wants dual v-cache dies if the processor isn't able to share cache between different CCDs. Outside of the chance you're just doing encoding or whatever that scales with cache and just want 20% more performance on a 16 core chip as is. Not saying that isn't a legit desire either but I don't see the huge need for it. In games and anything 1t bound its not gonna matter and it would still likely be slower than the 9800x3d and its singular cache if threads still bounce between dies.

And yes sure in an ideal world threads don't jump between the CCDs, but if that were the case then why would vcache or not matter anyways? If scheduling were perfect clock bound threads would always stay on the regular die and cache bound ones on the stacked die. However we all know this isn't how it works. And as such why wouldn't there be a performance hit with threads bouncing between two cache dies? Data movement is not free. Though I do wish there were any epyc-x gaming benchmarks out there, it would be enlightening to see if having v-cache on every die helps compared to a single CCD.

In the world where 2 cache dies were faster on average, AMD would be shipping SKUs like that instead of the split die model they currently have. I literally see no reason for them to leave money on the table outside of something like, facts. If they could build a chip that was 5% faster than a 9950x3d in its real config, they would absolutely be building that instead while also giving it a higher MSRP to compensate for having 5 chips instead of 4. But in the current GMI interconnect scheme for zen 5, its just not there I don't believe.

 

[Win2012R2]

I really don't know why anyone wants dual v-cache dies if the processor isn't able to share cache between different CCDs.

L3 are "shared" to ensure cache coherency of the whole chip via Infinity Fabric on IOD - this has got high latency, which is why it is ideal to have big L3 cache on each chiplet, this way there is much bigger chance workloads run on each chiplet will fit THEIR stuff into their local L3. Otherwise why would AMD create Genoa-X with extra cache on all chiplets, for mugs? It was priced only like 10% extra by the way, clearly tech is cheap enough.

Fitting 2 chiplets is already solved problem, there is zero difference (other than BOM price) if both of those chiplets are with extra L3, it only makes sense to keep one of them if this is same old same old Intel segmentation approach, big companies never change.

Games might not benefit much from it, but in this setup I could run a demanding game on chiplet 1 whilst running some work stuff on chiplet 2 that I can check from time to time alt-tabbing, with more L3 on second chiplet things would run far smoother this way, I am certainly prepared to pay $150-200 for it to get max results.

 

[adroc_thurston]

L3 are shared to ensure cache coherency of the whole chip via Infinity Fabric on IOD

They're coherent but not shared.

 

[Win2012R2]

They're coherent but not shared.

Yes, I've (later) put "shared" into double quotes.

More local L3 is good, price is cheap, it was done before for servers, freq diff is now far smaller, Turin-X scrapped, so what's the bloody problem offering it? It will make great server chip also - this extra cache will offset limits of 2 memory channels and slower perf with 4 ECC DIMMs.

 

[adroc_thurston]

so what's the bloody problem offering it

margin.

price is cheap

anything but.

this extra cache will offset limits of 2 memory channels

It will not.

 

[Win2012R2]

anything but.

From memory Genoa-X 96 cores was like just over a grand over extra for 12x extra 3D cache chiplets, that's very cheap per chiplet - 100 bucks?

 

[adroc_thurston]

From memory Genoa-X 96 cores was like just over a grand over extra for 12x extra 3D cache chiplets, that's very cheap per chiplet - 100 bucks?

List prices are NOT real prices. Forget about them.

 

[igor_kavinski]

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[Win2012R2]

List prices are NOT real prices. Forget about them.

I am talking about retail pricing that I could see, poor peasants like myself don't get hyperscaler discounts

 

[adroc_thurston]

I am talking about retail pricing that I could see, poor peasants like myself don't get hyperscaler discounts

We're not talking hyperscaler discounts.
You buy a system, not a CPU.

 

[DrMrLordX]

Turin-X scrapped

Really? When did that happen?

You buy a system, not a CPU.

Unless you're Mark.

 

[adroc_thurston]

When did that happen?

Somewhere this year when MS opted for MI300C for HPC refresh instead.

 

[DrMrLordX]

Somewhere this year when MS opted for MI300C for HPC refresh instead.

So is this a packaging bottleneck?

 

[techjunkie123]

Somewhere this year when MS opted for MI300C for HPC refresh instead.

Any plans for an MI325C with z5 chiplets?

 

[igor_kavinski]

So is this a packaging bottleneck?

I guess high capacity HBM is more useful.

 

[Win2012R2]

You buy a system, not a CPU.

I buy CPUs, Genoa-X retail price was just a grand over normal 96 core, that was 10-12%, on a system basis when you throw in RAM/nvmes etc that's even smaller increase, but in any case I was talking about AMD's money here - if they were getting only 100 bucks extra for each of the 12 3D chiplets then it's not expensive for them to do it at all.

 

[adroc_thurston]

So is this a packaging bottleneck?

No, just a product choice.

Any plans for an MI325C with z5 chiplets?

No.

I buy CPUs, Genoa-X retail price was just a grand over normal 96 core, that was 10-12%, on a system basis when you throw in RAM/nvmes etc that's even smaller increase, but in any case I was talking about AMD's money here - if they were getting only 100 bucks extra for each of the 12 3D chiplets then it's not expensive for them to do it at all.

Well the point is that you buy server stuff from your favorite OEM/ODM were CPU price varies. A lot.