Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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tsamolotoff

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May 19, 2019
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Yes. Yes. Give up. Give into dismay. That is the way. That is how you get closer to appeasing Darth Lisa with your fealty
Apathy is death, yada yada.

It's not dismay, I've already did full power run and posted the result here, but I think it was removed by either mods or some automod (as it contained a link to blender benchmark database). Thanks to x3d limits, CPU doesn't go above 1.1v in multicore loads (it is usually well below that), so we have to keep faith in our cacheless brethren
 
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gaav87

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Apr 27, 2024
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I can say without even running it that my CPU would be below that, I think total score for full power run was around 580 (if you sum all these values). It is actually interesting whether Z5 scales beyond these 160W, as it seems Z4 starts to face severe diminishing returns at this cutoff
Slug results:
7950x ~617,38 / 230W no-PBO
This ~678,1 / 160W ~10% increase
~715 minimum at 230w seems resonable if it has same clock eff. as 7950x
 
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Hail The Brain Slug

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Oct 10, 2005
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But sadly its still alittle unclear to me if the 7950X3D are benefiting from the v-cache on CCD0 in blender, or if its all down to voltage tuning for that SKU, since it seems to outperform the 7950X in the powerlimited scenario we're looking at in this thread.
My 7950X clocks 2.5-2.7GHz effective clocks at 60W PPT, ~30-31W core power.
My 7950X3D clocks 3.0-3.2GHz effective clocks at 60W PPT, ~28-29W core power.

The V$ might help some but it's mostly the V/F curve. If I undid the memory tuning on my 7950X3D and went straight EXPO I'd have a couple more watts to increase clocks a little more.
 

Josh128

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Oct 14, 2022
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Zen 5 IHS shows 2023 date. Disqus commenter Senpai noted the visible code seems to indicate 15th week of 2023. Thats over a year ago. Strange. Maybe because its got an old IOD?

 

Josh128

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Oct 14, 2022
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Wild speculation here. Turin is 3nm 16 core Zen 5c as far as we know. Based on MLIDs rather legit looking slide that called for 10-15% IPC for Zen 5, 4&3 nm variants, it also called out a new 16 core CCX. Guessing thats what Turin is.

What if that 3nm 16core CCX CCD was designed with X3D vias on it? Wouldnt it be something if at some point they surprise with a 16 core unified L3 X3D 3nm chip? Depending on clocks, seems like it could be a potent SKU.
 
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StefanR5R

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Dec 10, 2016
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They held it back!!! :eek:
As AMD said to TPU, they are a software shop now. Perhaps they want to debut Zen 5 with a really stable AGESA at launch, for once.

Wild speculation here. Turin is 3nm 16 core Zen 5c as far as we know. Based on MLIDs rather legit looking slide that called for 10-15% IPC for Zen 5, 4&3 nm variants, it also called out a new 16 core CCX. Guessing thats what Turin is.

What if that 3nm 16core CCX CCD was designed with X3D vias on it? Wouldnt it be something if at some point they surprise with a 16 core unified L3 X3D 3nm chip? Depending on clocks, seems like it could be a potent SKU.
3nm 16c CCX is for Turin-dense only (are the rumors saying). Turin proper is 4nm 8c CCX like Granite Ridge (but allegedly at a higher stepping). V-cache is for the classic CCDs only, not for the dense ones, just like in the current 9004 generation (Genoa/ Genoa-X, vs. cache-reduced Bergamo and Siena).
 

Josh128

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Oct 14, 2022
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As AMD said to TPU, they are a software shop now. Perhaps they want to debut Zen 5 with a really stable AGESA at launch, for once.


3nm 16c CCX is for Turin-dense only. Turin proper is 4nm 8c CCX like Granite Ridge (but allegedly at a higher stepping). V-cache is for the classic CCDs only, not for the dense ones, just like in the current 9004 generation (Genoa/ Genoa-X, vs. cache-reduced Bergamo and Siena).

Sure, thats how it was done last gen, but whos to say it wasnt designed with this option in mind for the future? 16 core Zen 4 CCD was already possible on 5/4nm. 3nm should be quite a bit more dense. Whats the extra density used for? Just smaller silicon and reduced power only?
 

StefanR5R

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Whats the extra density used for?
I don't know. But to me, it seems reasonable to assume that there will be only a single 16c CCX physical design in the Zen 5 generation, and that this one will be for "cloud native" server products primarily. For client (desktop in particular), a physical design needs to allow for high peak clocks. In contrast, a design which is supposed to be targeted to hyperscalers first and foremost will trade peak clocks for density.

AMD is supplying the desktop with server-derived designs and mobile-derived designs. Ultimately, that's what the other desktop CPU makers do too. Don't hold your breath for a high core count desktop exclusive design.
 

StefanR5R

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@Josh128, PS: Of course I too am curious how their 16c CCX (and the alleged Zen 6 32c CCX) is going to look like. But one thing is for certain: The larger a core complex topology is, the higher the lastlevel cache latencies, and with it the core-to-core latencies, are going to be. The shrink to 3nm may help in this regard though.
 

Hail The Brain Slug

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Oct 10, 2005
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It's not the copyright date but the mention "BY 2315PGY" that's strange. That would indicate 15th week of 2023.
Very strange there would even exist a retail etched sample from so long ago. It doesn't seem like it's necessarily one of the review samples, that article is kind of all over the place saying bitwit kyle "found it on a plane". The photos of the actual review samples have the details blurred on the IHS.

I checked, Zen 4 reviews had ~2226 date samples, so only ~13 week old samples. But this sample appears to be 65 weeks old. Over a year older than the review samples from last time.